$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Forming a conductive structure in a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0397763 (1999-09-15)
발명자 / 주소
  • Ronald A. Weimer
  • Yongjun Jeff Hu
  • Pai Hung Pan
  • Deepa Ratakonda
  • James Beck
  • Randhir P. S. Thakur
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Trop, Pruner & Hu, P.C.
인용정보 피인용 횟수 : 60  인용 특허 : 24

초록 ▼

A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide n

대표청구항 ▼

1. A method of forming a multi-layer conductive structure in a semiconductor device, the method comprising:forming a first layer containing silicon; depositing a metal layer over the first layer; and annealing the metal layer in an ambient having a composition selected from a group consisting of nit

이 특허에 인용된 특허 (24) 인용/피인용 타임라인 분석

  1. Bulucea Constantin ; Kerr Daniel C., Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect tra.
    상세보기
  2. Kim Young-sun,KRX ; Lee Nae-in,KRX ; Ko Dae-hong,KRX, Gate electrode for semiconductor device.
    상세보기
  3. Hu Yongjun, Gate electrode stack with diffusion barrier.
    상세보기
  4. Fazan Pierre C. ; Chan Hiang C., Gate having a barrier of titanium silicide.
    상세보기
  5. Prall Kirk D. (Boise ID) Sandhu Gurtej S. (Boise ID) Meikle Scott G. (Boise ID), Low resistance device element and interconnection structure.
    상세보기
  6. Gronet Christian M. ; Knoot Peter A. ; Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Satheesh, Method and apparatus for insitu vapor generation.
    상세보기
  7. Suzuki Toshiya (Kawasaki JPX) Ohba Takayuki (Kawasaki JPX) Jinnouchi Shimpei (Tokyo JPX) Murakami Seishi (Tokyo JPX), Method for deposition of a refractory metal nitride and method for formation of a conductive film containing a refractor.
    상세보기
  8. Maiti Bikas ; Paulson Wayne ; Heddleson James, Method for forming a high voltage gate dielectric for use in integrated circuit.
    상세보기
  9. Nenyei Zsolt,DEX ; Lerch Wilfried,DEX ; Sommer Helmut,DEX, Method for rapid thermal processing (RTP) of silicon substrates.
    상세보기
  10. Horai Masataka (Saga JPX) Adachi Naoshi (Saga JPX) Nishikawa Hideshi (Saga JPX) Sano Masakazu (Saga JPX), Method of annealing a semiconductor wafer in a hydrogen atmosphere to desorb surface contaminants.
    상세보기
  11. Keller David J. (Boise ID), Method of etching WSix films.
    상세보기
  12. Huang Jenn Ming,TWX ; Su Chi-Wen,TWX ; Wu Chung-Cheng,TWX ; Chen Shui-Hung,TWX, Method of forming a metal gate for CMOS devices using a replacement gate process.
    상세보기
  13. Riseman Jacob (Poughkeepsie NY), Method of making integrated circuits using metal silicide contacts.
    상세보기
  14. Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Sathees, Method of oxidizing a substrate in the presence of nitride and oxynitride films.
    상세보기
  15. Hames Greg A., Oxide etch barrier formed by nitridation.
    상세보기
  16. Fujimura Shuzo (Tokyo JPX) Takeuchi Tetsuya (Koube JPX) Miyanaga Takeshi (Ono JPX) Nakano Yoshimasa (Akashi JPX) Matoba Yuji (Koube JPX), Plasma treating method using hydrogen gas.
    상세보기
  17. Bai Gang ; Fraser David B., Polycide film.
    상세보기
  18. Ma Yi ; Merchant Sailesh Mansinh ; Oh Minseok ; Roy Pradip Kumar, Polycide gate structure with intermediate barrier.
    상세보기
  19. Fazan Pierre C. (Boise ID) Figura Thomas A. (Boise ID), Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack.
    상세보기
  20. Lin Chenyong Frank, Self-aligned storage node definition in a DRAM that exceeds the photolithography limit.
    상세보기
  21. Arima Satoshi,JPX, Semiconductor device with gate electrodes having conductive films.
    상세보기
  22. Dennison Charles H. (Boise ID) Walker Michael A. (Boise ID), Semiconductor processing methods of forming stacked capacitors.
    상세보기
  23. Agnello Paul David ; Cabral ; Jr. Cyril ; Grill Alfred ; Jahnes Christopher Vincent ; Licata Thomas John ; Roy Ronnen Andrew, Tasin oxygen diffusion barrier in multilayer structures.
    상세보기
  24. Torres Joaquim (Saint Martin le Vinoux FRX) Palleau Jean (Uriage FRX) Bourhila Noureddine (Echirolles FRX), Tungsten silicide self-aligned formation process.
    상세보기

이 특허를 인용한 특허 (60) 인용/피인용 타임라인 분석

  1. Weimer,Ronald A., Capacitor structures with oxynitride layer between capacitor plate and capacitor dielectric layer.
    상세보기
  2. Hu, Yongjun; Thakur, Randhir P. S.; DeBoer, Scott, Conductor layer nitridation.
    상세보기
  3. Hu, Yongjun; Thakur, Randhir P.S.; DeBoer, Scott, Conductor layer nitridation.
    상세보기
  4. Pan, Pai-Hung, Doped silicon diffusion barrier region.
    상세보기
  5. Tanabe, Yoshikazu; Asano, Isamu; Yoshida, Makoto; Yamamoto, Naoki; Saito, Masayoshi; Natsuaki, Nobuyoshi, Fabrication process of a semiconductor integrated circuit device.
    상세보기
  6. Tanabe, Yoshikazu; Asano, Isamu; Yoshida, Makoto; Yamamoto, Naoki; Saito, Masayoshi; Natsuaki, Nobuyoshi, Fabrication process of a semiconductor integrated circuit device.
    상세보기
  7. Tanabe, Yoshikazu; Asano, Isamu; Yoshida, Makoto; Yamamoto, Naoki; Saito, Masayoshi; Natsuaki, Nobuyoshi, Fabrication process of a semiconductor integrated circuit device.
    상세보기
  8. Tanabe,Yoshikazu; Asano,Isamu; Yoshida,Makoto; Yamamoto,Naoki; Saito,Masayoshi; Natsuaki,Nobuyoshi, Fabrication process of a semiconductor integrated circuit device.
    상세보기
  9. Tanabe,Yoshikazu; Asano,Isamu; Yoshida,Makoto; Yamamoto,Naoki; Saito,Masayoshi; Natsuaki,Nobuyoshi, Fabrication process of a semiconductor integrated circuit device.
    상세보기
  10. Weimer, Ronald A.; Hu, Yongjun Jeff; Pan, Pai Hung; Ratakonda, Deepa; Beck, James; Thakur, Randhir P. S., Forming a conductive structure in a semiconductor device.
    상세보기
  11. Rouh, Kyong-Bong; Na, Shang-Koon; Eun, Yong-Seok; Kim, Su-Ho; Kim, Tae-Han; Lee, Mi-Ri, Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and conductive structure of the same.
    상세보기
  12. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  13. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  14. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  15. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  16. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  17. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  18. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  19. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  20. Tanabe,Yoshikazu; Sakai,Satoshi; Natsuaki,Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  21. Tanabe,Yoshikazu; Sakai,Satoshi; Natsuaki,Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  22. Tanabe,Yoshikazu; Sakai,Satoshi; Natsuaki,Nobuyoshi, Method for fabricating semiconductor integrated circuit device.
    상세보기
  23. Tanabe, Yoshikazu; Sakai, Satoshi; Natsuaki, Nobuyoshi, Method for fabricating semiconductor integrated circuit drive using an oxygen and hydrogen catalyst.
    상세보기
  24. Lee, Byung Hak, Method for forming gate electrode of semiconductor device.
    상세보기
  25. Kim, Yong-Soo; Oh, Su-Jin, Method for manufacturing gate structure for use in semiconductor device.
    상세보기
  26. Weimer, Ronald A, Method of composite gate formation.
    상세보기
  27. Weimer,Ronald A, Method of composite gate formation.
    상세보기
  28. Weimer,Ronald A, Method of composite gate formation.
    상세보기
  29. Weimer,Ronald A., Method of composite gate formation.
    상세보기
  30. Wu, Chii-Ming; Wang, Mei-Yun; Chang, Chih-Wei; Hsieh, Chin-Hwa; Shue, Shau-Lin; Fu, Chu-Yun; Hsu, Ju-Wang; Tsai, Ming-Huan; Chiu, Yuan-Hung, Method of forming contact plug on silicide structure.
    상세보기
  31. Wu,Chii Ming; Chang,Chih Wei; Shue,Shau Lin; Hsu,Ju Wang; Tsai,Ming Huan, Method of forming contact plug on silicide structure.
    상세보기
  32. Chan,Bor Wen; Shieh,Jyu Horng; Tao,Hun Jan, Method of forming silicided gate structure.
    상세보기
  33. Wu,Chii Ming; Lin,Cheng Tung; Wang,Mei Yun; Chang,Chih Wei; Shue,Shau Lin, Method of forming silicided gate structure.
    상세보기
  34. Weimer,Ronald A., Method of improved high K dielectric--polysilicon interface for CMOS devices.
    상세보기
  35. Weimer,Ronald A., Method of improved high K dielectric-polysilicon interface for CMOS devices.
    상세보기
  36. Weimer,Ronald A., Method of improved high K dielectric-polysilicon interface for CMOS devices.
    상세보기
  37. Yokota, Yoshitaka; Tam, Norman L.; Ramachandran, Balasubramanian; Ripley, Martin John, Method of improving oxide growth rate of selective oxidation processes.
    상세보기
  38. Yokota, Yoshitaka; Tam, Norman; Ramachandran, Balasubramanian; Ripley, Martin John, Method of improving oxide growth rate of selective oxidation processes.
    상세보기
  39. Nomachi, Akiko; Harakawa, Hideaki, Method of manufacturing semiconductor device.
    상세보기
  40. Abbott,Todd R., Methods of forming a transistor with an integrated metal silicide gate electrode.
    상세보기
  41. Abbott,Todd R., Methods of forming a transistor with an integrated metal silicide gate electrode.
    상세보기
  42. Hu,Yongjun Jeff, Methods of forming metal silicide.
    상세보기
  43. Lee, Yong Sun; Lee, Jai Dong; Kim, Bong Hyun; Kang, Man Sug; Kim, Jung Hwan; Shin, Hyun Jin; Yoo, Won Seok; Shin, Seung Mok, Methods of manufacturing a semiconductor device.
    상세보기
  44. Yamazaki, Shunpei; Takayama, Toru; Maruyama, Junya; Goto, Yuugo; Ohno, Yumiko, Peeling method and method for manufacturing display device using the peeling method.
    상세보기
  45. Yamazaki, Shunpei; Takayama, Toru; Maruyama, Junya; Goto, Yuugo; Ohno, Yumiko, Peeling method and method for manufacturing display device using the peeling method.
    상세보기
  46. Yamazaki, Shunpei; Takayama, Toru; Maruyama, Junya; Goto, Yuugo; Ohno, Yumiko, Peeling method and method for manufacturing display device using the peeling method.
    상세보기
  47. Yamazaki, Shunpei; Takayama, Toru; Maruyama, Junya; Goto, Yuugo; Ohno, Yumiko, Peeling method and method for manufacturing display device using the peeling method.
    상세보기
  48. Yamazaki, Shunpei; Takayama, Toru; Maruyama, Junya; Goto, Yuugo; Ohno, Yumiko, Peeling method and method for manufacturing display device using the peeling method.
    상세보기
  49. Tanabe, Yoshikazu; Nagahama, Toshiaki; Natsuaki, Nobuyoshi; Nakatsuka, Yasuhiko, Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process.
    상세보기
  50. Tanabe, Yoshikazu; Nagahama, Toshiaki; Natsuaki, Nobuyoshi; Nakatsuka, Yasuhiko, Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process.
    상세보기
  51. Tanabe, Yoshikazu; Nagahama, Toshiaki; Natsuaki, Nobuyoshi; Nakatsuka, Yasuhiko, Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process.
    상세보기
  52. Tanabe, Yoshikazu; Yamamoto, Naoki; Mitani, Shinichiro; Hanaoka, Yuko, Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device.
    상세보기
  53. Bunyk, Paul I, RSFQ Batcher-banyan switching network.
    상세보기
  54. Tam, Norman; Trowbridge, Teresa, RTP process chamber pressure control.
    상세보기
  55. Hu,Yongjun Jeff, Semiconductor constructions and electronic systems comprising metal silicide.
    상세보기
  56. Yamamoto, Naoki; Tanabe, Yoshikazu, Semiconductor integrated circuit device and method for manufacturing the same.
    상세보기
  57. Yamamoto, Naoki; Tanabe, Yoshikazu, Semiconductor integrated circuit device and method for manufacturing the same.
    상세보기
  58. Yamamoto, Naoki; Tanabe, Yoshikazu, Semiconductor integrated circuit device and method for manufacturing the same.
    상세보기
  59. Wu,Chii Ming; Lin,Cheng Tung; Wang,Mei Yun; Chang,Chih Wei; Shue,Shau Lin, Semiconductor structure including silicide regions and method of making same.
    상세보기
  60. Herring,Robert B.; Porter,Cole; Dodwell,Travis; Nazareno,Ed; Ratliff,Chris; Chatterji,Anindita, System and method for hydrogen-rich selective oxidation.
    상세보기

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로