[특허]Semiconductor device and method of manufacturing the same

Semiconductor device and method of manufacturing the same 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/48 H01L-023/52 H01L-029/40
출원번호	US-0915398 (1997-08-20)
우선권정보	JP-0219987 (1996-08-21)
발명자 / 주소	Minakshisundaran Balasubramanian Anand JP
출원인 / 주소	Kabushiki Kaisha Toshiba JP
대리인 / 주소	Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보	피인용 횟수 : 37 인용 특허 : 7

초록 ▼

In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.

대표청구항 ▼

1. A semiconductor device comprising:a semiconductor substrate; a semiconductor element formed on said semiconductor substrate; a first insulating layer formed above said semiconductor element and having a flat upper surface, a plurality of first grooves and a second groove formed therein, said plurality of first grooves separating a plurality of insulating pillars in a lattice pattern, each pillar having a flat upper surface; a first layer of conductive material formed in the first grooves, said first layer of conductive material functioning as a bonding pad and having a flat upper surface; a passivation layer formed above said first insulating layer and having an opening exposing said first layer of conductive material; a second layer of conductive material formed in the second groove forming a wiring layer; a second insulating layer formed between said first insulating layer and said passivation layer, said second insulating layer being of a material having a high etch selectivity compared to the passivation layer, said second insulating layer having an opening coinciding with said opening in said passivation layer; wherein the upper surfaces of said first insulating layer, said insulating pillars, and said first layer of conductive material are coplanar; the second groove comprising a depression for containing the wiring layer and a hole containing a contact plug, the hole being located directly under the depression, the second groove thereby having a dual-damascene structure.

이 특허에 인용된 특허 (7)

Wollesen Donald L. (Saratoga CA), High conductivity interconnection line.
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Harada Shigeru (Hyogo-ken JPX) Hagi Kimio (Hyogo-ken JPX) Tsumura Kiyoaki (Hyogo-ken JPX), Process of passivating a semiconductor device bonding pad by immersion in O₂ or O₃ solution<.
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Harada Shigeru (Hyogo-ken JPX) Endoh Takemi (Hyogo-ken JPX) Ishida Tomohiro (Hyogo-ken JPX), Semiconductor device and method of manufacturing thereof.
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Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Kimura Hiroshi (Hyogo JPX) Wakamiya Wataru (Hyogo JPX) Tanaka Yoshinori (Hyogo JPX), Semiconductor device having bonding pad comprising buffer layer.
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Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Kimura Hiroshi (Hyogo JPX) Wakamiya Wataru (Hyogo JPX) Tanaka Yoshinori (Hyogo JPX), Semiconductor device having bonding pad comprising buffer layer.
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Langley Rodney C. (Boise ID), Semiconductor device with improved bond pads.
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Cochran William T. (New Tripoli PA) Garcia Agustin M. (Allentown PA) Hills Graham W. (Allentown PA) Yeh Jenn L. (Macungie PA), Semiconductor devices having multi-level metal interconnects.
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이 특허를 인용한 특허 (37)

Li, Shaoping; Rudy, Steven C.; Bertero, Gerardo A.; Ding, Yunfei; Beaudry, Christopher L., Apparatus and method for middle shield connection in magnetic recording transducers.
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Li, Shaoping; Bertero, Gerardo A.; Rudy, Steven C.; He, Shihai; Mao, Ming; Xi, Haiwen; Ganesan, Srikanth; Leng, Qunwen; Yi, Ge; Xiao, Rongfu; Liu, Feng; Wang, Lei, Apparatuses and methods for providing thin shields in a multiple sensor array.
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Li, Shaoping; Bertero, Gerardo A.; Mallary, Michael L.; Yi, Ge; Rudy, Steven C., Connection schemes for a multiple sensor array usable in two-dimensional magnetic recording.
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Yamamoto, Koji; Kumamoto, Nobuhisa; Matsumoto, Muneyuki, Damascene interconnection and semiconductor device.
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Yamamoto,Koji; Kumamoto,Nobuhisa; Matsumoto,Muneyuki, Damascene interconnection and semiconductor device.
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Agarwala,Birendra N.; Coker,Eric M.; Correale, Jr.,Anthony; Rathore,Hazara S.; Sullivan,Timothy D.; Wachnik,Richard A., Dual-damascene metallization interconnection.
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Li, Shaoping; Rudy, Steven C.; Yi, Ge; Bertero, Gerardo A.; Leng, Qunwen; Mao, Ming, Electrical connection arrangement for a multiple sensor array usable in two-dimensional magnetic recording.
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Li, Shaoping; Bertero, Gerardo A.; Yi, Ge; Mallary, Michael L.; Leng, Qunwen; Champion, Eric J., Multiple sensor array usable in two-dimensional magnetic recording.
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Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
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Wu,Bing Chang; Wang,Kun Chih; Chao,Mei Ling; Chen,Shiao Shien, Semiconductor chip capable of implementing wire bonding over active circuits.
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Wu,Bing Chang; Wang,Kun Chih; Chao,Mei Ling; Chen,Shiao Shien, Semiconductor chip capable of implementing wire bonding over active circuits.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
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연합인증

Semiconductor device and method of manufacturing the same 원문보기

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Semiconductor device and method of manufacturing the same 원문보기

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이 특허에 인용된 특허 (7)

이 특허를 인용한 특허 (37)

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