초록 ▼

General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and com

General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.

대표청구항 ▼

1. A single instruction multiple data stream (SIMD) machine with a controller (SP) and at least two processing elements (PEs), each PE in said SIMD machine comprising:an arithmetic unit which receives at least two operands from a register file; instruction control lines derived from a registered ins

1. A single instruction multiple data stream (SIMD) machine with a controller (SP) and at least two processing elements (PEs), each PE in said SIMD machine comprising:an arithmetic unit which receives at least two operands from a register file; instruction control lines derived from a registered instruction that was received from the SP in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction; the arithmetic unit producing a result and a latched arithmetic scalar condition state; a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state; a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state; an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state; and an ACF latch for storing the previous state and feeding the previous state back to the ACF generation unit.