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Programmable voltage divider and method for testing the impedance of a programmable element 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0770096 (2001-01-23)
발명자 / 주소
  • Donald M. Morgan
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dorsey & Whitney LLP
인용정보 피인용 횟수 : 10  인용 특허 : 29

초록

A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled

대표청구항

1. A semiconductor device, comprising:a circuit including a programmable voltage divider having normal and test modes of operation, the programmable voltage divider comprising: first and second supply nodes; a divider node operable to provide a data value; a first divider element coupled between sai

이 특허에 인용된 특허 (29)

  1. Eltoukhy Abdelshafy A. (San Jose CA), Apparatus and method determining the resistance of antifuses in an array.
  2. Kummer Karl T. (Doylestown PA), Apparatus and method for detection of an open thermocouple in a process control network.
  3. McCollum John L. (Saratoga CA), Apparatus and method for measuring programmed antifuse resistance.
  4. McCollum John L. (Saratoga CA), Apparatus and method for measuring programmed antifuse resistance.
  5. Aso Makoto (Anjo JPX) Kondo Akira (Okazaki JPX), Apparatus for failure identification for use in vehicle occupant protecting system.
  6. Michel Thomas J. (Hialeah FL) Clarke Robert (Cooper City FL), Bridge-balancing system for measuring extremely low currents.
  7. McClure David C. (Denton TX) Teel Thomas A. (Carrollton TX), Circuit for providing a compensated bias voltage.
  8. Chen Zhi Q. (5N ; Hibben Apt. ; Faculty Rd. Princeton NJ 08540) Chen Yi-Hong (5N ; Hibben Apt. ; Faculty Rd. Princeton NJ 08540), Electrical data recording and retrieval based on impedance variation.
  9. Miller Roger L. (San Jose CA) Regan Timothy T. (San Jose CA), Failsafe voltage regulator with warning signal driver.
  10. Watanabe Makoto (Nisshin JPX) Masegi Mitsuhiko (Nukata-gun JPX), Failure diagnostic apparatus and method for a resistor element.
  11. Schreck John F. (Houston TX) Truong Phat C. (Houston TX) Tatman David (Missouri City TX), Integrated circuit fuse-link tester and test method.
  12. Miller Francis M. (Snyder NY), Method and apparatus for testing a conductivity sensing circuit.
  13. Riggio ; Jr. Salvatore R. (Boca Raton FL), Method and apparatus for testing electrical and electronic circuits.
  14. Pyun Do-Sun,KRX, Method and apparatus for testing internal circuit.
  15. Goetting F. Erich (Cupertino CA) Kondapalli Venu (San Jose CA) Schultz David P. (San Jose CA), Method and system for measuring antifuse resistance.
  16. Allen William J. (10120 Lockwood Dr. Cupertino CA 95014-2614), Method for programming antifuses for reliable programmed links.
  17. Thiel David W. (Acton MA), Method of and apparatus for electrical short testing and the like.
  18. Birkner John M. (Portola Valley CA) Martin David T. (Santa Clara CA) Wong Richard J. (Milpitas CA), Method of determining an electrical characteristic of an antifuse and apparatus therefor.
  19. Rao G. R. Mohan, Methods and circuits for single-memory dynamic cell multivalue data storage.
  20. Li Li-Chun ; Watters Lynne ; Fang Sharlin, Programmable circuits.
  21. Shimanek Schuyler E. (Albuquerque NM) Anderson Alma (Rio Rancho NM), Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, val.
  22. Morgan Donald M., Programmable voltage divider and method for testing the impedance of a programmable element.
  23. Tsuchiya Fumio (Kodaira JPX) Matsubara Kiyoshi (Kodaira JPX), Semiconductor integrated circuit device with built-in memories.
  24. Lawrence Archer R. ; Little Jack C., Synchronous memory test method.
  25. Lawrence Archer R ; Little Jack C, Synchronous memory test system.
  26. Janke Donald R. (Milwaukee WI) Rodrian James A. (Grafton WI), System for calibrating a line isolation monitor.
  27. Blankenship Timothy L. (Palm Bay FL) Nolan ; III Joseph G. (San Jose CA), Test circuitry for testing fuse link programmable memory devices.
  28. Necoechea R. Warren (Milpitas CA), Tri-state driver circuit for automatic test equipment.
  29. Talreja Sanjay S. (Folsom CA) Bauer Mark E. (Cameron Park CA) Frary Kevin W. (Fair Oaks CA) Kwong Phillip M. L. (Folsom CA), Write verify schemes for flash memory with multilevel cells.

이 특허를 인용한 특허 (10)

  1. Simmons, Tuyet Ngoc; Patra, Madan; Rau, Prasad, Method and apparatus for testing a controlled impedance buffer.
  2. Khoury, Elie Georges, Method for measuring fuse resistance in a fuse array.
  3. Kim,Young Sik, Probe-base storage apparatus having redundancy cantilevers.
  4. Kenkare,Prashant U.; Waldrip,Jeffrey W.; Hoefler,Alexander B., Programmable cell.
  5. Hwang, Mi Hyun, Programming circuit using antifuse.
  6. Lee, Kang-Seol, Semiconductor device and operating method thereof.
  7. Erickson, Karl R.; Paone, Phil C.; Paulsen, David P.; Sheets, II, John E.; Uhlmann, Gregory J., System for testing charge trap memory cells.
  8. Erickson, Karl R.; Paone, Phil C.; Paulsen, David P.; Sheets, II, John E.; Uhlmann, Gregory J., System for testing charge trap memory cells.
  9. Wheeler, Alan R., Testing method for permanent electrical removal of an integrated circuit output.
  10. Wheeler,Alan R., Testing method for permanent electrical removal of an intergrated circuit output after packaging.
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