초록 ▼

An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltag

An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.

대표청구항 ▼

1. A semiconductor device operating under reception of an external power-supply voltage comprising:first and second data lines for transmitting a data signal having two data levels one of which corresponds to a first voltage; and a plurality of memory cells for holding said data signal, each of said

1. A semiconductor device operating under reception of an external power-supply voltage comprising:first and second data lines for transmitting a data signal having two data levels one of which corresponds to a first voltage; and a plurality of memory cells for holding said data signal, each of said plurality of memory cells including a storage node for storaging the data level of said data signal, a data transfer gate for electrically connecting said storage node with one of said first and second data lines in response to activation of a word line set to a second voltage higher than said first voltage, and a data-line equalizing circuit for setting said first and second data lines to one same predetermined voltage in response to a control signal, said control signal being set to a third voltage higher than said external power-supply voltage and lower than said second voltage under activation.