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A chip for a device such as a computer includes a media access controller and an embedded processor. The embedded processor is programmed to function as a web server and provide network manageability information to a network manager. The embedded processor is also programmed to function as a LAN con

A chip for a device such as a computer includes a media access controller and an embedded processor. The embedded processor is programmed to function as a web server and provide network manageability information to a network manager. The embedded processor is also programmed to function as a LAN controller. When a packet is received by the media access controller, the embedded processor examines a destination address of the packet and routes the packet to an appropriate end point. Packets having a first unique destination address are routed to a host interface (and eventually to a host processor), and packets having a second unique address are routed to the embedded processor-functioning-as-web server. Thus, the chip allows network management and local area network communications to be performed over a single physical interface.

대표청구항 ▼

1. A network controller for a device, the device including a host processor, the controller comprising:a media access controller for accepting packets having unique first and second destination addresses; a buffer for temporarily buffering the packets accepted by the media access controller; a host

1. A network controller for a device, the device including a host processor, the controller comprising:a media access controller for accepting packets having unique first and second destination addresses; a buffer for temporarily buffering the packets accepted by the media access controller; a host interface; a dedicated processor programmed to function as a web server, the dedicated processor being further programmed to determine the destination addresses of packets in the buffer, route the packets having the first destination address to the dedicated processor, and route the packets having the second destination address to the host processor; flash memory including a first plurality of executable instructions and a second plurality of executable instructions, the first plurality of instructions, when executed, instructing the dedicated processor to function as the web server, the second plurality of instructions, when executed, instructing the dedicated processor to read the destination addresses of packets in the buffer and route the packets; a DRAM for storing the packets having the first destination address; and a memory interface for the Flash memory and the DRAM.