초록 ▼

The architecture of the inventive correlator is, in a preferred embodiment, an array of correlation cells each containing a delay pipe, a math unit and an accumulator. An array of these correlation cells are tiled together to allow simultaneous processing by all cells. The array is disposed so that

The architecture of the inventive correlator is, in a preferred embodiment, an array of correlation cells each containing a delay pipe, a math unit and an accumulator. An array of these correlation cells are tiled together to allow simultaneous processing by all cells. The array is disposed so that each cell accumulates an output value in a result surface. There is no electrical limit to the number of correlation cells that may be tiled together. A preferred embodiment uses nine cells tiled together into a 3.times.3 correlation result surface. Other embodiments have been tested in accordance with the present invention having twenty-five cells tiled together into a 5.times.5 correlation result surface. A stream of compare pixel values is presented to the array wherein each compare pixel value is presented to each cell concurrently. A reference memory supplies the appropriate reference pixel values to the cells to enable all calculations for that compare pixel value to be done concurrently. The results of those calculations are summed in each cell's accumulator. The process is repeated for each compare pixel value in the stream. When all compare pixel values in the stream have been processed, the values in the accumulators are compared. Generally, the lowest value is accepted as the correlation value.

대표청구항 ▼

1. A method for performing low latency correlation, comprising the steps of:(a) representing a pixelated reference image as a reference array of reference pixel values and a pixelated compare image as a compare array of compare pixel values; (b) indexing movement of the compare array over the refere

1. A method for performing low latency correlation, comprising the steps of:(a) representing a pixelated reference image as a reference array of reference pixel values and a pixelated compare image as a compare array of compare pixel values; (b) indexing movement of the compare array over the reference array to an result surface, each different location that the compare array may be overlaid on the reference array defining a patch; (c) one by one for all compare pixel values in the compare array, presenting a same compare pixel value simultaneously to each patch; (d) concurrently for each of said compare pixel value presentations, computing patch values from said presented compare pixel values and corresponding tagged reference pixel values; (e) successively for compare pixel values presented in step (c), accumulating patch values computed in step (d) separately for each patch; and (f) when patch values have been accumulated in step (e) for all compare pixel values presented according to step (c), identifying a correlation value by analyzing said result surface according to predetermined criteria.