초록 ▼

A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by dual-gated transistors. The dual gates of the tran

A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by dual-gated transistors. The dual gates of the transistors are biased to modify the threshold voltage of the transistors (Vt). This design provides fast switching capability for low power battery operated CMOS circuits and systems. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

대표청구항 ▼

1. A method of fabricating an inverter, the method comprising:forming a first transistor, the first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/

1. A method of fabricating an inverter, the method comprising:forming a first transistor, the first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate formed on a first one of the opposing sidewall surfaces, and having a second gate formed on a second one of the opposing sidewall surfaces; forming a second transistor, the second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate formed on a first one of the opposing sidewall surfaces, and having a second gate formed on a second one of the opposing sidewall surfaces; forming a third transistor, the third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate formed on a first one of the opposing sidewall surfaces, and having a second gate formed on a second one of the opposing sidewall surfaces; forming a fourth transistor, the fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate formed on a first one of the opposing sidewall surfaces, and having a second gate formed on a second one of the opposing sidewall surfaces; forming an electrical contact between collector/drain regions of the second and third transistors to provide an output for the inverter; forming a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter; forming the second gate of the first transistor to couple to the first gate of the first transistor; and forming the second gate of the fourth transistor to couple to the first gate of the first transistor.