초록 ▼

Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al-Cu alloy top pad metal layers are descri

Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al-Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al-Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al-Cu bond layer or region is placed on top of the underlying copper pad metal. This Al-Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.

대표청구항 ▼

1. A method for fabricating wire bond pads for applications in MOSFET and CMOS semiconductor devices using copper dual damascene, a method comprising:providing a substrate, wafer or substrate module; providing a first level of conducting wiring being defined and over said substrate; depositing a pas

1. A method for fabricating wire bond pads for applications in MOSFET and CMOS semiconductor devices using copper dual damascene, a method comprising:providing a substrate, wafer or substrate module; providing a first level of conducting wiring being defined and over said substrate; depositing a passivating layer over the first level of conducting wiring; depositing a first insulating layer of dielectric, forming a first intermetal dielectric layer (IMD), over the passivating layer; depositing a second insulating layer of dielectric, forming a second intermetal dielectric layer (IMD), over the first insulating layer of dielectric (IMD); patterning and etching the intermetal dielectric layers (IMD), and said passivating layer, forming a dual damascene trench/via opening, exposing regions of the first level of conducting wiring; depositing and patterning a cap layer over the second intermetal dielectric layer (IMD); depositing a first blanket conductive metal barrier layer or first barrier layer, over the patterned cap layer, and into the trench/via openings, and over said exposed regions of the first level of conducting wiring; depositing a blanket copper layer over the first barrier layer, and filling the trench/via opening; polishing back by chemical mechanical polishing (CMP) the excess copper and first barrier layer material, stopping on the cap layer, forming a dual damascene inlaid copper in the trench/via; etching back selectively by wet etching the top layer of the inlaid copper within the trench/via, forming a recessed copper within the trench/via and partially recessed trench/via opening; etching copper oxide on the top layer of the recessed copper within the trench/via, that may be present, by hydrogen or ammonia plasma gas treatment; depositing a second blanket conductive metal barrier layer or second barrier layer, over the recessed copper within the trench/via, and over the patterned cap layer; depositing a blanket layer of Al-Cu alloy over the second barrier layer, and filling the partially recessed trench/via opening; annealing thermally with forming gas the layer of Al-Cu alloy, enhancing alloy formation; polishing back by chemical mechanical polishing (CMP) the Al-Cu alloy and second barrier layer material, stopping on the cap layer, forming a region of inlaid Al-Cu alloy bond pad, over a copper dual damascene interconnect trench/via, suitable for wire bonding and soldering without further passivation.