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[미국특허] Method and apparatus for hierarchical restructuring of computer code 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/44
출원번호 US-0647862 (1996-05-15)
발명자 / 주소
  • Mauricio Breternitz, Jr.
  • Roger A. Smith
출원인 / 주소
  • Motorola Inc.
대리인 / 주소
    Joanna P. Gariazzo
인용정보 피인용 횟수 : 63  인용 특허 : 16

초록 ▼

A compiler (142) constructs (FIGS. 14-32) a Reduced Flowgraph (RFG) from computer source code (144). The RFG is used to instrument (FIG. 36) code (142). An object module is created (146) and executed (148). Resulting path frequency counts are written to a counts file (154). A compiler (158) uses the

대표청구항 ▼

1. A computer-implemented method for hierarchical restructuring of computer code using runtime statistics, said method comprising:a) building a hierarchical representation of a Control Flow Graph (CFG) in terms of Single Entry/Single Exit (SESE) regions corresponding to execution flow of a computer

이 특허에 인용된 특허 (16) 인용/피인용 타임라인 분석

  1. Hasebe Takayuki (Kawasaki JPX) Akiyama Ryota (Kawasaki JPX) Yoshioka Makoto (Kawasaki JPX), Electronic data protection system.
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  2. Goebel Kurt J., Functional unit switching for the allocation of registers.
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  3. Breternitz ; Jr. Mauricio ; Smith Roger A., Method and apparatus for sequencing computer instruction execution in a data processing system.
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  4. Iwayama Noboru,JPX ; Torii Naoya,JPX ; Hasebe Takayuki,JPX ; Takenaka Masahiko,JPX ; Matsuda Masahiro,JPX, Method and device for utilizing data content.
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  5. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
    상세보기
  6. Lorie Raymond A. (San Jose CA) Strong ; Jr. Hovey R. (San Jose CA), Method for conditional branch execution in SIMD vector processors.
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  7. Pettis Karl W. (San Jose CA) Hansen Robert C. (Santa Clara CA), Method for optimizing computer code to provide more efficient execution on computers having cache memories.
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  8. Wiecek Cheryl A. (Westford MA), Methods and apparatus for transforming machine language program control into high-level language constructs by manipulat.
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  9. Alpert Alan I. (Hopewell Junction NY) Greenstein Paul G. (Fishkill NY) Rodell John T. (Wappingers Falls NY) Raghayan Ramanathan (Austin TX), Optimizing assembled code for execution using execution statistics collection, without inserting instructions in the cod.
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  10. Heisch Randall R. (Austin TX) Kilpatrick Paul J. (Austin TX), Profile-based preprocessor for optimizing programs.
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  11. Alpert Alan I. (Hopewell Junction NY) Greenstein Paul G. (Fishkill NY) Rodell John T. (Wappingers Falls NY) Raghavan Ramanathan (Austin TX), Program construct and methods/systems for optimizing assembled code for execution.
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  12. Goebel Kurt J. (Los Gatos CA), Register allocation by decomposing, re-connecting and coloring hierarchical program regions.
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  13. Koblenz Brian D. (Seattle WA) Callahan ; II Charles D. (Mercer Island WA), Register allocation methods having upward pass for determining and propagating variable usage information and downward p.
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  14. Hasebe Takayuki,JPX ; Torii Naoya,JPX ; Iwayama Noboru,JPX ; Takenaka Masahiko,JPX ; Matsuda Masahiro,JPX, Software charging system and software data utilization permitting device.
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  15. Hasebe Takayuki (Kawasaki JPX) Akiyama Ryota (Kawasaki JPX) Yoshioka Makoto (Kawasaki JPX), Storage medium for preventing an illegal use by a third party.
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  16. Spix George A. (Eau Claire WI) Wengelski Diane M. (Eau Claire WI) Hawkinson Stuart W. (Eau Claire WI) Johnson Mark D. (Eau Claire WI) Burke Jeremiah D. (Eau Claire WI) Thompson Keith J. (Eau Claire W, System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel executi.
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