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Surge preventing circuit for an insulated gate type transistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02H-009/00
출원번호 US-0334741 (1999-06-17)
우선권정보 JP-0173413 (1998-06-19); JP-0116245 (1999-04-23)
발명자 / 주소
  • Kenji Kouno JP
출원인 / 주소
  • Denso Corporation JP
대리인 / 주소
    Harness, Dickey & Pierce, PLC
인용정보 피인용 횟수 : 31  인용 특허 : 17

초록

A first Zener diode group, connected between drain and gate terminals of a power MOSFET, causes breakdown in response to a surge voltage applied to the drain terminal. A resistor, provided between the gate terminal of the power MOSFET and a gate control unit, prevents current from flowing from the d

대표청구항

1. A surge preventing circuit for an insulated gate type transistor with high-voltage and low-voltage terminals, one of which is connected to an electric load, and a gate terminal connected to a gate control unit, said surge preventing circuit comprising:a first Zener diode having one end connected

이 특허에 인용된 특허 (17)

  1. Robb Stephen P. (Tempe AZ) Phipps John P. (Phoenix AZ) Gadberry Michael D. (Tempe AZ), Avalanche stress protected semiconductor device having variable input impedance.
  2. Mosher Dan M. (Plano TX) Latham Larry (Garland TX) Todd Bob (Plano TX) Blanton Cornelia H. (Plano TX) Trogolo Joe R. (Plano TX) Cotton David R. (Plano TX), Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate.
  3. Matsushita Tsutomu (Yokohama JPX) Mihara Teruyoshi (Yokosuka JPX), Integrated circuit device having vertical MOS provided with Zener diode.
  4. Tokoro Nobuhiro (West Newbury MA) Becker Richard C. (Ipswich MA), Ion source.
  5. Ishikawa Fukuo (Kariya JPX) Konishi Shuuichi (Nagoya JPX) Nakamura Katsumi (Okazaki JPX) Ikemoto Hideyuki (Anjo JPX) Ishida Toshio (Kariya JPX), Load drive apparatus including power transistor protection circuit from overcurrent.
  6. Kobayashi Takashi,JPX ; Fujihira Tatsuhiko,JPX ; Takeuchi Shigeyuki,JPX ; Kondo Yoshiki,JPX ; Furuhata Shoichi,JPX, MOS type semiconductor device.
  7. Mihara Teruyoshi (Yokosuka JPX) Hirota Yukitsugu (Kamakura JPX) Hiramoto Yukio (Tokyo JPX) Matsushita Tsutomu (Yokohama JPX), MOSFET device.
  8. Mosher Dan M. (Plano TX) Blanton Cornelia H. (Plano TX) Trogolo Joe R. (Plano TX) Latham Larry (Garland TX) Cotton David R. (Plano TX) Todd Bob (Plano TX), Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circ.
  9. Palara Sergio (Acitrezza ITX), Monolithic integrated structure to protect a power transistor against overvoltage.
  10. Wodarczyk Paul J. (Mountaintop PA) Jones Frederick P. (Mountaintop PA) Neilson John M. S. (Norristown PA) Yedinak Joseph A. (Wilkes-Barre PA), Power MOSFET transistor circuit with active clamp.
  11. Fujimoto Hiroshi (Kariya JPX) Yamaoka Masami (Anjo JPX) Tsuzuki Yukio (Aichi JPX), Power semiconductor apparatus.
  12. Imai Hiroshi (Kariya JPX), Power semiconductor device with a gate withstand-voltage test terminal.
  13. Suda Minoru (Takasaki JPX) Nakasu Masatoshi (Shibukawa JPX) Iijima Tetsuo (Maebashi JPX), Power transistor device including power transistors in darlington connection and zener diode which is coupled between co.
  14. Watanabe Toshio (Tokyo JPX), Semiconductor circuit having input protective circuit.
  15. Sakamoto Kozo (Hechiouji JPX) Yoshida Isao (Nishitama-gun JPX) Morikawa Masatoshi (Hachiouji JPX) Ohtaka Shigeo (Takasaki JPX) Tsunoda Hideki (Akishima JPX), Semiconductor device having a protection circuit, and electronic system including the same.
  16. Phipps John P. (Phoenix AZ) Robb Stephen P. (Tempe AZ) Sutor Judy L. (Chandler AZ) Terry Lewis E. (Phoenix AZ), Semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage.
  17. Kumagai Naoki (Kawasaki JPX), Semiconductor device including overvoltage protective circuit.

이 특허를 인용한 특허 (31)

  1. Mathieu, Denis René Pierre, Apparatus and method for control of semiconductor switching devices.
  2. Smith, Gregory J., Circuit for preventing high voltage damage to a MOSFET switch in series with an inductor when current flow is interrupted.
  3. Chen, Zi-Ping; Ker, Ming-Dou, Diode and applications thereof.
  4. Ogawa, Kazutoshi; Ishikawa, Katsumi, Drive circuit for switching device.
  5. Kasuya,Hirokazu; Numazaki,Koji; Saitou,Mitsuhiro; Fukuda,Yutaka; Ueda,Nobumasa, Driving apparatus of H bridge circuit and protection method of the same.
  6. Li, Xia; Kim, Daeik Daniel; Yang, Bin; Kim, Jonghae; Perry, Daniel Wayne, Dual mode transistor.
  7. Wang, Wen-Tai; Ho, Ming-Jing, ESD protection circuit for negative-powered integrated circuit.
  8. Wu, Yi Hsun; Lee, Jian Hsing, ESD protection circuit with low parasitic capacitance.
  9. Hayashi, Yutaka, ESD protection circuit, semiconductor device, on-vehicle electronic device, and on-vehicle electronic system.
  10. Hatzilambrou, Mark; Leung, Chester; Walia, Rajan; Liang, Lien Wee; Rustagi, Subhash C.; Radhakrishnan, M K, ESD protection system for high frequency applications.
  11. Okushima, Mototsugu, Electrostatic protection circuit.
  12. Okushima, Mototsugu, Electrostatic protection circuit.
  13. Snowdon, Kenneth, High-side output transistor circuit.
  14. Ueno, Katsunori, Internal combustion engine igniter semiconductor device.
  15. Hussein,Khalid Hassan; Shinohara,Masuo, Power conversion device.
  16. Kobayashi, Atsushi; Takasu, Hisashi, Power semiconductor device driving circuit.
  17. Sako, Hiromi, Protection circuit for semiconductor switching element, and power conversion device.
  18. Takasu, Hisashi; Kobayashi, Atsushi, Semiconductor apparatus.
  19. Fukuhara, Jun, Semiconductor device.
  20. Harada, Yuichi; Naito, Tatsuya; Toyoda, Yoshiaki, Semiconductor device.
  21. Toyoda, Yoshiaki, Semiconductor device and method of manufacturing semiconductor device.
  22. Yannou, Jean-Marc; Van Zwol, Johannes; Savin, Emmanuel, Semiconductor device with improved ESD protection.
  23. Chan, Wing-Chor; Hu, Chih-Min; Chen, Li-Fan, Semiconductor device, start-up circuit having first and second circuits and a single voltage output terminal coupled to a second node between the semiconductor unit and the first circuit, and operating method for the same.
  24. Hayashida, Yoko; Hayano, Kiminori; Furuta, Hiroshi, Semiconductor integrated circuit device and method for designing the same.
  25. Arashima,Yoshinori; Abe,Hirofumi; Takahashi,Shigeki, Semiconductor output circuit.
  26. Urakawa, Yukihiro, Stacked MOSFET protection circuit.
  27. Zoels, Thomas Alois; Carastro, Fabio, Switch controller for adaptive reverse conduction control in switch devices.
  28. Liljegren, Dan; Haraldsson, Oscar, Switch protection i auxiliary resonant circuit.
  29. McIntosh, James; Looby, Christy, Systems and methods for driving a load under various power conditions.
  30. Acharya, Parag Vishwanath; Magdum, Vijay Sukumar, Systems, methods, and apparatus for limiting voltage across a switch.
  31. Kilroy, Donald G., Two-level lightning protection circuit.
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