초록 ▼

The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plat

The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plate has a top surface exposed outside a resin body used for encapsulating the chip and the heat sink, and a bottom surface opposed to the top surface. The planar plate further has a thick portion formed on the bottom surface relative to the position of the chip, wherein there is a gap formed between the end surface of the thick portion and the chip to prevent the heat sink from directly contacting with the chip, and an end surface of the thick portion has a plurality of flow channels formed along the flowing direction of the molding gate to avoid the formation of void in the gap so as to increase the yield rate of products.

대표청구항 ▼

1. A semiconductor package comprising:a substrate; at least one chip adhered to and electrically connected to said substrate; a heat sink having a planar plate and a support for supporting said planar plate to a height for positioning said planar plate above said chip, wherein said planar plate has

1. A semiconductor package comprising:a substrate; at least one chip adhered to and electrically connected to said substrate; a heat sink having a planar plate and a support for supporting said planar plate to a height for positioning said planar plate above said chip, wherein said planar plate has a top surface exposed outside a resin body used for encapsulating said chip and said heat sink, and a bottom surface opposed to said top surface and having a thick portion formed relative to the position of said chip, further an end surface of the thick portion having a plurality of flow channels, wherein there is a gap formed between said end surface of said thick portion and said chip; and a plurality of conductive members connected to said substrate and electrically connecting said chip with an external device.