초록 ▼

A multi-die integrated circuit (IC) assembly and method for constructing the same are disclosed. Briefly described, the IC assembly can be constructed with a semiconductor die, a layer of die-attach material, and a flip-chip die. The semiconductor die may contain circuit elements disposed across a t

A multi-die integrated circuit (IC) assembly and method for constructing the same are disclosed. Briefly described, the IC assembly can be constructed with a semiconductor die, a layer of die-attach material, and a flip-chip die. The semiconductor die may contain circuit elements disposed across a top surface of the die. The flip-chip die may be oriented such that circuit elements are disposed across a bottom surface of the flip-chip die. The die-attach material may contact and bond the non-circuit element surfaces of the semiconductor die an the flip-chip die (i.e., the bottom surface of the semiconductor die and the top surface of the flip-chip die). This configuration permits the close arrangements of input/output circuit drivers along the entire perimeter of each of the dies. A method for constructing the multi-die IC assembly is also presented. The method can be broadly summarized by the following steps: arranging a semiconductor die such that circuit components are found on the upper surface of the die; arranging a flip-chip such that circuit components are found on the lower surface of the flip-chip; and introducing a layer of die-attach material such that it contacts and bonds the lower surface of the semiconductor die and the upper surface of the flip-chip.

대표청구항 ▼

1. A multiple-die integrated circuit assembly, comprising:a substrate having a first level, a second level, and a third level, the first and second levels of the substrate defining a multiple-level cavity configured to receive the multiple-die integrated circuit assembly, the first level and second

1. A multiple-die integrated circuit assembly, comprising:a substrate having a first level, a second level, and a third level, the first and second levels of the substrate defining a multiple-level cavity configured to receive the multiple-die integrated circuit assembly, the first level and second levels of the substrate each comprising a plurality of conductive pads, wherein the conductive pads on the first level of the substrate are associated with a solder bump; a first semiconductor die having a first surface and an opposing second surface, the first surface having a plurality of conductive pads arranged to contact a plurality of the conductive pads on the first level of the substrate; and a first conductor coupled to one of the conductive pads on the first semiconductor die and to a first conductive pad on the second level of the substrate.