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Updating placement during technology mapping 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0322262 (1999-05-28)
발명자 / 주소
  • Arnold Ginetti FR
출원인 / 주소
  • Cadence Design Systems, Inc.
대리인 / 주소
    Lyon & Lyon LLP
인용정보 피인용 횟수 : 19  인용 특허 : 16

초록

A method for estimating the position of a matched cell takes into account the interconnectivities of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights are given to

대표청구항

1. A method of determining a location for a matched cell, the matched cell encompassing a set of matched nodes, at least one of the matched nodes being connected to at least one non-matched node, each matched node having a position associated therewith, the method comprising the steps of:assigning a

이 특허에 인용된 특허 (16)

  1. Poirot Frank,FRX ; Roane Ramine ; Tarroux Gerard,FRX, Automatic synthesis of integrated circuits employing boolean decomposition.
  2. Horstmann Paul William ; Rosser Thomas Edward ; Sawkar Prashant Srinivasrao, Computer program product for enabling a computer to remove redundancies using quasi algebraic methods.
  3. Dey Sujit (Plainsboro NJ) Potkonjak Miodrag (Plainsboro NJ) Rothweiler Steven (Kunkletown PA), Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits.
  4. Schaefer Thomas J. ; Shur Robert D., Enhanced dynamic programming method for technology mapping of combinational logic circuits.
  5. Do Cuong (San Jose CA) Wei Ruey-Sing (Fremont CA), Hierarchical ordering of logical elements in the canonical mapping of net lists.
  6. Lehman Eric ; Grodstein Joel Joseph ; Harkness Heather ; Kodandapani Kolar, Implicit tree-mapping technique.
  7. Trimberger Stephen M. (San Jose CA) Chene Mon-Ren (Cupertino CA), Logic placement using positionally asymmetrical partitioning method.
  8. Matsumoto Kazuhiko,JPX ; Shinsha Takao,JPX ; Hayashi Nobuyuki,JPX ; Sakaki Hiromoto,JPX ; Tandai Miyako,JPX ; Yamada Yasunori,JPX ; Nakata Takahiro,JPX ; Moriwaki Kaoru,JPX ; Koshishita Junji,JPX, Logic synthesis method and system with intermediate circuit files.
  9. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.
  10. Scepanovic Ranko ; Andreev Alexander E. ; Raspopovic Pedja, Memory-saving method and apparatus for partitioning high fanout nets.
  11. Pixley Carl ; Park Jaehong, Method for determining functional equivalence between design models.
  12. Khouja Adel (Saratoga CA) Krishnamoorthy Shankar (Sunnyvale CA) Mailhot Frederic G. (Palo Alto CA) Meier Stephen F. (Sunnyvale CA), Method for electronic memory management during estimation of average power consumption of an electronic circuit.
  13. Damiano Robert F. (Hopewell Junction NY) Drumm Anthony D. (Rochester MN) Edwards Michael K. (Rochester MN) Kanzelman Robert L. (Rochester MN) McCarthy Kathy M. (Rochester MN), Method for mapping in logic synthesis by logic classification.
  14. Damarla T. Raju ; Su Wei, Methods and computer programs for minimizing logic circuit design using identity cells.
  15. Scepanovic Ranko ; Koford James S. ; Kudryavtsev Valeriy B.,RUX ; Aleshin Stanislav V.,RUX ; Andreev Alexander E.,RUX ; Podkolzin Alexander S.,RUX, Physical design automation system and method using monotonically improving linear clusterization.
  16. Cox William D. (San Jose CA) Lehmann Eric E. (San Francisco CA) Lulla Mukesh T. (Santa Clara CA) Nathamuni Venkatesh R. (San Jose CA), Select set-based technology mapping method and apparatus.

이 특허를 인용한 특허 (19)

  1. Amaru, Luca Gaetano; Vuillod, Patrick; Luo, Jiong, Exact delay synthesis.
  2. Makino,Osamu, Library creating device and interconnect capacitance estimation system using the same.
  3. Li,Hung Chun, Method and an apparatus to improve hierarchical design implementation.
  4. Singh,Deshanand; Manohararajah,Valavan; Schabas,Karl, Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays.
  5. Nauts, Claire; Ginetti, Arnold, Method and system for timing and area driven binary and/or matching.
  6. Ginetti, Arnold, Method for updating a placed and routed netlist.
  7. Ginetti, Arnold; Kohli, Vikas; Kukal, Taranjit Singh, Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics.
  8. Ginetti, Arnold; Kukal, Taranjit Singh; Kohli, Vikas, Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics.
  9. Ginetti, Arnold; Durrill, Steven; Kukal, Taranjit Singh, Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness.
  10. Ginetti, Arnold; Kohli, Vikas; Kukal, Taranjit Singh, Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics.
  11. Kukal, Taranjit Singh; Durrill, Steven; Bhattacharyya, Utpal; Sharma, Amit, Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs.
  12. Kukal, Taranjit Singh; Durrill, Steven; Bhattacharyya, Utpal; Sharma, Amit, Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs.
  13. Kukal, Taranjit Singh; Durrill, Steven R.; Ginetti, Arnold, Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics.
  14. Kukal, Taranjit Singh; Singh, Balvinder; Durrill, Steven R.; Ginetti, Arnold; Khanna, Vikrant; Dabral, Abhishek; Sharma, Madhur; Gupta, Nikhil; Bhattacharya, Ritabrata, Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design.
  15. Ginetti, Arnold, Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designs.
  16. Ginetti, Arnold; Pei, Yuan-Kai; Su, Yu-Chi, Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations.
  17. Majumder, Chayan; Ginetti, Arnold; Manglani, Chandra Prakash; Kumar, Amit, Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs.
  18. Donelly, Ross A.; Naylor, William C.; Fu, Michael, Multiple pass optimization for automatic electronic circuit placement.
  19. Lu, Aiguo; Pavisic, Ivan; Raspopovic, Pedja, Netlist resynthesis program based on physical delay calculation.
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