초록

A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

대표청구항 ▼

1. A method of manufacturing an integrated circuit comprising:a. providing a wafer having an inter-level dielectric film and a barrier layer; b. depositing a seed layer of copper on said barrier layer; c. electroplating copper to a thickness sufficient to fill any valleys in said inter-level dielect

1. A method of manufacturing an integrated circuit comprising:a. providing a wafer having an inter-level dielectric film and a barrier layer; b. depositing a seed layer of copper on said barrier layer; c. electroplating copper to a thickness sufficient to fill any valleys in said inter-level dielectric film and cover an entire top surface of said wafer; d. chemical mechanical polishing said top surface to remove i) any excess portions of copper caused by said electroplating and ii) selected portions of said inter-level dielectric film; e. depositing a layer of CrO on said polished top surface to cover remaining portions of said copper; f. depositing a passivation layer on said layer of CrO and portions of said inter-level dielectric film; and g. etching said passivation layer to form a via that exposes a selected portion of said layer of CrO.