초록 ▼

Integrated circuitry and methods of forming integrated circuitry are described. In one aspect, a hole is formed in a semiconductor wafer. In a preferred implementation, the hole extends through the entire wafer. Subsequently, conductive material is formed within the hole and interconnects with integ

Integrated circuitry and methods of forming integrated circuitry are described. In one aspect, a hole is formed in a semiconductor wafer. In a preferred implementation, the hole extends through the entire wafer. Subsequently, conductive material is formed within the hole and interconnects with integrated circuitry which is formed proximate at least one of a front and back wafer surface. According to one aspect of the invention, integrated circuitry is formed proximate both front and back surfaces. In a preferred implementation, a plurality of holes are formed through the wafer prior to formation of the integrated circuitry. In accordance with a preferred implementation, formation of the conductive material within the hole takes place through formation of a first material within the hole. A second material is formed over the first material, with at least the second material being electrically conductive. The wafer is exposed to conditions which are effective to cause the second material to replace the first material. In another preferred implementation, the hole has an interior surface and prior to formation of the conductive material therein, a dielectric layer is formed within the hole proximate the interior surface.

대표청구항 ▼

1. Integrated circuitry comprising:a semiconductive wafer fragment having front and back surfaces; integrated circuitry disposed over both the front and back surfaces; at least one passageway extending entirely through the wafer fragment between the front and back surfaces, the passageway being defi

1. Integrated circuitry comprising:a semiconductive wafer fragment having front and back surfaces; integrated circuitry disposed over both the front and back surfaces; at least one passageway extending entirely through the wafer fragment between the front and back surfaces, the passageway being defined by an interior surface comprising material of the wafer fragment, the passageway extending into the wafer fragment in a direction which is generally normal relative to the front and back surfaces and defining a pair of opposing parallel sidewalls extending between the front and back surfaces, the passageway having an aspect ratio of between 75 and 80, the passageway being lined with an electrically insulating material, the electrically insulating material comprising a silicon nitride layer in physical contact with material of the wafer fragment within the passageway, the electrically insulating material comprising a silicon dioxide layer over and in physical contact with the silicon nitride layer, the silicon nitride layer and the silicon dioxide layer having a combined thickness of from 50 nanometers to 100 nanometers; and conductive material comprising conductive aluminum disposed within the at least one passageway and in physical contact with the silicon dioxide layer, the conductive aluminum electrically interconnecting the integrated circuitry disposed over the front and back surfaces, the passageway not containing any semiconductive wafer fragment material.