초록 ▼

A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced

A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

대표청구항 ▼

1. A method of fabricating a double gate MOSFET device comprising the steps of:a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface, b) providing an etchant mask on the major surface, c) patterning the etchan

1. A method of fabricating a double gate MOSFET device comprising the steps of:a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface, b) providing an etchant mask on the major surface, c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer, d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer, the channel being a fin with a top surface and two opposing sidewalls, e) forming a gate dielectric on sidewalls of the channel region, f) depositing gate material over the etchant mask and the gate dielectric, g) selectively masking and etching the gate material to form a gate on the top surface and sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask, h) forming dielectric spacers between the gate and the source and drain regions, and i) doping the source and drain regions.