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Semiconductor substrate and method of manufacturing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0238571 (1999-01-28)
우선권정보 JP-0023066 (1998-02-04); JP-0370316 (1998-12-25)
발명자 / 주소
  • Yutaka Akino JP
  • Tadashi Atoji JP
출원인 / 주소
  • Canon Kabushiki Kaisha JP
대리인 / 주소
    Fitzpatrick, Cella, Harper & Scinto
인용정보 피인용 횟수 : 101  인용 특허 : 9

초록

A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral

대표청구항

1. A method of manufacturing a semiconductor substrate comprising a support member, an insulation layer arranged on the support member and a semiconductor layer arranged on the insulation layer, the outer peripheral extremity of the semiconductor layer being located inside the outer peripheral extre

이 특허에 인용된 특허 (9)

  1. Ito Yatsuo (Sanai-cho 7 Jyouetsu-shi Niigata-ken JPX) Abe Takao (477-19 Yanase ; Annaka-shi ; Gunma-ken JPX) Takei Tokio (Hara219-5 Kawanakajima-machi ; Nagano-shi ; Nagano-ken JPX) Nakamura Susumu (, Bonded wafer and method of manufacturing it.
  2. Ogawa Tadashi,JPX ; Ishii Akihiro,JPX ; Nakayoshi Yuichi,JPX, Method for fabricating an SOI substrate.
  3. Ito Tatsuo (Joetsu JPX) Uchiyama Atsuo (Chiisagata JPX) Fukami Masao (Nagano JPX), Method for preparing a substrate for semiconductor devices.
  4. Takei Tokio,JPX ; Nakamura Susumu,JPX ; Nakazawa Kazushi,JPX, Method of manufacturing a bonding substrate.
  5. Golland David I. (Chesterfield MO) Craven Robert A. (Olivette MO) Bartram Ronald D. (Webster Groves MO), Process for stripping outer edge of BESOI wafers.
  6. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  7. Miyawaki Mamoru,JPX ; Kawasumi Yasushi,JPX ; Inoue Shunsuke,JPX ; Akino Yutaka,JPX ; Koizumi Toru,JPX ; Kohchi Tetsunobu,JPX, Semiconductor device made using processing from both sides of a workpiece.
  8. Yonehara Takao (Atsugi JPX), Semiconductor member and process for preparing semiconductor member.
  9. Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.

이 특허를 인용한 특허 (101)

  1. Or-Bach, Zvi; Wurman, Ze'ev, 3D integrated circuit with logic.
  2. Sekar, Deepak C.; Or-Bach, Zvi; Cronquist, Brian, 3D memory semiconductor device and structure.
  3. Or-Bach, Zvi, 3D semiconductor device.
  4. Or-Bach, Zvi, 3D semiconductor device.
  5. Or-Bach, Zvi; Wurman, Zeev, 3D semiconductor device.
  6. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, 3D semiconductor device and structure.
  7. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, 3D semiconductor device and structure.
  8. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, 3D semiconductor device and structure.
  9. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, 3D semiconductor device and structure.
  10. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, 3D semiconductor device and structure.
  11. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; Wurman, Ze'ev; Lim, Paul, 3D semiconductor device and structure with back-bias.
  12. Or-Bach, Zvi; Wurman, Ze'ev, 3D semiconductor device including field repairable logics.
  13. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Wurman, Zeev, 3D semiconductor device, fabrication method and system.
  14. Or-Bach, Zvi; Widjaja, Yuniarto, 3DIC system with a two stable state memory and back-bias region.
  15. Or-Bach, Zvi; Wurman, Zeev, Automation for monolithic 3D devices.
  16. Lee, Sang-Yun, Bonded semiconductor structure and method of making the same.
  17. Nakano, Masatake; Mitani, Kiyoshi; Tomizawa, Shinichi, Bonded wafer producing method and bonded wafer.
  18. Xiang, Hua; Bae, Indeog; Jung, Sung Jin; Qin, Ce; Fu, Qian; Yamaguchi, Yoko, Hybrid stair-step etch.
  19. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Integrated circuit device and structure.
  20. Or-Bach, Zvi; Wurman, Zeev, Method for design and manufacturing of a 3D semiconductor device.
  21. Or-Bach, Zvi, Method for developing a custom device.
  22. Or-Bach, Zvi; Sekar, Deepak C., Method for fabricating novel semiconductor and optoelectronic devices.
  23. Cronquist, Brian; Beinglass, Isreal; de Jong, Jan Lodewijk; Sekar, Deepak C.; Or-Bach, Zvi, Method for fabrication of a semiconductor device and structure.
  24. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Isreal; de Jong, Jan Lodewijk; Sekar, Deepak C., Method for fabrication of a semiconductor device and structure.
  25. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Method for fabrication of a semiconductor device and structure.
  26. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of a semiconductor device and structure.
  27. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of a semiconductor device and structure.
  28. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of a semiconductor device and structure.
  29. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Wurman, Ze'ev, Method for fabrication of a semiconductor device and structure.
  30. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, Method for fabrication of a semiconductor device and structure.
  31. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of configurable systems.
  32. Bae, In Deog; Fu, Qian, Method for forming stair-step structures.
  33. Fu, Qian; Yu, Hyun-Yong, Method for forming stair-step structures.
  34. Fu, Qian; Yu, Hyun-Yong, Method for forming stair-step structures.
  35. Yokokawa, Isao; Noto, Nobuhiko, Method for manufacturing SOI wafer.
  36. Tobisaka, Yuji; Akiyama, Shoji; Kubota, Yoshihiro; Kawai, Makoto; Nagata, Kazutoshi, Method for producing hybrid substrate, and hybrid substrate.
  37. Trickett, Douglas M; Yamashita, Atsushi, Method for thinning a bonding wafer.
  38. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; Wurman, Ze'ev; Lim, Paul, Method of constructing a semiconductor device and structure.
  39. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Isreal; de Jong, Jan Lodewijk; Sekar, Deepak C., Method of fabricating a semiconductor device and structure.
  40. Kim, Chang Gyu; Kim, Wan Shick, Method of forming a protective step on the edge of a semiconductor wafer.
  41. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian; Wurman, Ze'ev, Method of forming three dimensional integrated circuit devices using layer transfer technique.
  42. Or-Bach, Zvi; Widjaja, Yuniarto, Method of maintaining a memory state.
  43. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Method of manufacturing a semiconductor device and structure.
  44. Sekar, Deepak C.; Or-Bach, Zvi, Method of manufacturing a semiconductor device with two monocrystalline layers.
  45. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, J. L.; Sekar, Deepak C.; Lim, Paul, Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer.
  46. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, Method of processing a semiconductor device.
  47. Ghyselen, Bruno, Method of smoothing the outline of a useful layer of material transferred onto a support substrate.
  48. Or-Bach, Zvi; Wurman, Zeev, Method to construct a 3D semiconductor device.
  49. Or-Bach, Zvi; Wurman, Ze'ev, Method to construct systems.
  50. Or-Bach, Zvi; Wurman, Ze'ev, Method to form a 3D semiconductor device.
  51. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian, Method to form a 3D semiconductor device and structure.
  52. Martin, Stephen L.; Oba, Shigeru; Suzuki, Yoshinori, Methods and computer program products for characterizing a crystalline structure.
  53. Zhou, Wei; Yu, Aibin; Ma, Zhaohui, Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems.
  54. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C., Monolithic three-dimensional semiconductor device and structure.
  55. Mikelson,Hans Peter; Lobos,George James, Process to form fine features using photolithography and plasma etching.
  56. Broekaart, Marcel; Migette, Marion; Molinari, Sébastien; Neyret, Eric, Progressive trimming method.
  57. Vineis, Christopher J.; Westhoff, Richard; Bulsara, Mayank, Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy.
  58. Sekar, Deepak C.; Or-Bach, Zvi, Self aligned semiconductor device and structure.
  59. Or-Bach, Zvi; Lim, Paul; Sekar, Deepak C., Semiconductor and optoelectronic devices.
  60. Or-Bach, Zvi; Sekar, Deepak, Semiconductor and optoelectronic devices.
  61. Or-Bach, Zvi; Sekar, Deepak C., Semiconductor and optoelectronic devices.
  62. Or-Bach, Zvi, Semiconductor device and structure.
  63. Or-Bach, Zvi, Semiconductor device and structure.
  64. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  65. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  66. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  67. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  68. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  69. Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  70. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C., Semiconductor device and structure.
  71. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C.; Lim, Paul, Semiconductor device and structure.
  72. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C.; Wurman, Zeev, Semiconductor device and structure.
  73. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, Semiconductor device and structure.
  74. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, Semiconductor device and structure.
  75. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, Semiconductor device and structure.
  76. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Semiconductor device and structure.
  77. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian, Semiconductor device and structure.
  78. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian, Semiconductor device and structure.
  79. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian; Lim, Paul, Semiconductor device and structure.
  80. Or-Bach, Zvi; Widjaja, Yuniarto; Sekar, Deepak C., Semiconductor device and structure.
  81. Or-Bach, Zvi; Wurman, Zeev, Semiconductor device and structure.
  82. Sekar, Deepak C.; Or-Bach, Zvi, Semiconductor device and structure.
  83. Sekar, Deepak C.; Or-Bach, Zvi, Semiconductor device and structure.
  84. Sekar, Deepak C; Or-Bach, Zvi; Lim, Paul, Semiconductor device and structure.
  85. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure.
  86. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Semiconductor device and structure for heat removal.
  87. Sekar, Deepak C.; Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure for heat removal.
  88. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, Semiconductor device and structure for heat removal.
  89. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Semiconductor devices and structures.
  90. Or-Bach, Zvi; Wurman, Zeev, Semiconductor devices and structures.
  91. Lee, Sang-Yun, Semiconductor memory device.
  92. Lee, Sang-Yun, Semiconductor memory device and method of fabricating the same.
  93. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Wurman, Zeev, Semiconductor system and device.
  94. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian; Wurman, Ze'ev, Semiconductor system and device.
  95. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, Semiconductor system, device and structure with heat removal.
  96. Yeh, Po-Chun; Tsai, Kan-Hsueh; Tsou, Chuan-Wei; Lee, Heng-Yuan; Liu, Hsueh-Hsing; Ho, Han-Chieh; Fu, Yi-Keng, Structure of epitaxial wafer and method of fabricating the same.
  97. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, J. L.; Sekar, Deepak C., System comprising a semiconductor device and structure.
  98. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C.; Wurman, Zeev, System comprising a semiconductor device and structure.
  99. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C.; Wurman, Zeev, System comprising a semiconductor device and structure.
  100. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk; Sekar, Deepak C.; Wurman, Zeev, System comprising a semiconductor device and structure.
  101. Lee, Sang-Yun, Three-dimensional integrated circuit structure.
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