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Semiconductor integrated circuit device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
출원번호 US-0987820 (2001-11-16)
우선권정보 JP-0182902 (1999-06-29)
발명자 / 주소
  • Koichiro Ishibashi JP
  • Kenichi Osada JP
출원인 / 주소
  • Hitachi, Ltd. JP
대리인 / 주소
    Mattingly, Stanger & Malur, P.C.
인용정보 피인용 횟수 : 67  인용 특허 : 2

초록

In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing proc

대표청구항

1. A semiconductor integrated circuit device comprising;a dynamic memory cell array, each memory cell having a transfer NMOS transistor and a capacitor, and a data input and output circuit having a first NMOS transistor, wherein the thickness of the gate film of said transfer NMOS transistor and sai

이 특허에 인용된 특허 (2)

  1. Leong Raymond M. (Los Altos CA), Method to implement a large resettable static RAM without the large surge current.
  2. Fujita Tetsuya,JPX ; Matsubara Gensoh,JPX ; Kuroda Tadahiro,JPX ; Sakurai Takayasu,JPX, Semiconductor integrated circuit device.

이 특허를 인용한 특허 (67)

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  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  19. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  20. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  21. Chan, Yuen H.; Hsu, Louis L.; Joshi, Rajiv V.; Wong, Robert Chi-Foon, Method to improve cache capacity of SOI and bulk.
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  23. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  25. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  26. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  27. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  28. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  29. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  37. Yamaoka, Masanao; Ishibashi, Koichiro; Matsui, Shigezumi; Osada, Kenichi, Semiconductor device.
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  53. Takahashi, Hiroyuki; Fukushi, Tetsuo, Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage.
  54. Takahashi, Hiroyuki; Fukushi, Tetsuo, Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage.
  55. Takahashi, Hiroyuki; Fukushi, Tetsuo, Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage.
  56. Takahashi, Hiroyuki; Fukushi, Tetsuo, Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage.
  57. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  58. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  59. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  63. Agata, Yasuhiro; Kawasaki, Toshiaki; Shirahama, Masanori; Nishihara, Ryuji; Sumi, Shinichi; Yamamoto, Yasue; Kikukawa, Hirohito, System LSI.
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