초록 ▼

Architecture, circuitry, and methods are provided for testing one or more integrated circuits which may be arranged upon a printed circuit board. The integrated circuits include sequential and combinatorial logic used by the integrated circuit during normal functioning thereof. Testing of that logic

Architecture, circuitry, and methods are provided for testing one or more integrated circuits which may be arranged upon a printed circuit board. The integrated circuits include sequential and combinatorial logic used by the integrated circuit during normal functioning thereof. Testing of that logic can occur by sending test vectors in parallel or serial form to input pins of the integrated circuit. The test results can either be read as a serial data stream or as a parallel-delivered data stream. If the test information and results occur in parallel fashion, than automated test equipment can be used which do not require compliance with having a single serial fed test vector input and test result output, normally found in a TAP application. A parallel/serial multiplexer is used to select whether the integrated circuit receives parallel or serial test vectors, and another parallel/serial multiplexer is used to select whether the test results are to be delivered in parallel or serial fashion. A test access port controller is linked to various boundary scan cells, and control signal generators within the controller orchestrate movement of test data or normal functional data into and from the integrated circuit core logic. Parallel fed test vectors can be shifted from the input cells as serial fed test vectors and then back to the input cells, where the test vectors can then be sent to the core logic among numerous conductors in parallel fashion. Likewise, the test results can be converted from a parallel to serial form and fed back to the output cells, whereupon the test results can be sent to the test equipment as parallel-delivered test results.

대표청구항 ▼

1. Test architecture, comprising:an integrated circuit having a plurality of input pins adapted to receive a parallel delivered test signal; a singular input pin adapted to receive a serial delivered test signal; and a first multiplexer coupled to directly present to a plurality of scan elements wit

1. Test architecture, comprising:an integrated circuit having a plurality of input pins adapted to receive a parallel delivered test signal; a singular input pin adapted to receive a serial delivered test signal; and a first multiplexer coupled to directly present to a plurality of scan elements within a core logic of the integrated circuit either the serial delivered test signal or the parallel delivered test signal converted to serial format.