$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Interconnection structure and method for fabricating same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0718010 (2000-11-21)
발명자 / 주소
  • David V. Horak
  • William A. Klaasen
  • Thomas L. McDevitt
  • Mark P. Murray
  • Anthony K. Stamper
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Schmeiser, Olsen & Watts
인용정보 피인용 횟수 : 40  인용 특허 : 22

초록

An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of

대표청구항

1. A method of forming an interconnection structure, the method comprising the steps of:depositing and patterning a first insulator to form an aperture opening to a substrate; depositing a first conductor and polishing the first conductor, thereby leaving the first conductor in the aperture; deposit

이 특허에 인용된 특허 (22)

  1. Beyer Klaus D. (Poughkeepsie NY) Hsu Louis L. (Fishkill NY) Kulkarni Subodh K. (Fishkill NY), Air-filled isolation trench with chemically vapor deposited silicon dioxide cap.
  2. Avanzino Steven (Cupertino CA) Erb Darrell M. (Los Altos CA) Cheung Robin (Cupertino CA) Klein Rich (Mountain View CA), Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines.
  3. Lin Charles W. C. (San Antonio TX) German Randy L. (Austin TX) Yee Ian Y. K. (Austin TX) Sigmond David M. (Austin TX), Detecting completion of electroless via fill.
  4. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
  5. Jeng Shin-puu ; Havemann Robert H., Interconnect capacitance between metal leads.
  6. Kepler Nick, Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias.
  7. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of fabricating a damascene structure for copper medullization.
  8. Yao Liang-Gi,TWX ; Tu Yeur-Luen,TWX ; Huang Sen-Huan,TWX ; Tsai Kwong-Jr,TWX ; Cherng Meng-Jaw,TWX, Method of fabricating a passivation layer for integrated circuits.
  9. Lee Tong-Hsin,TWX, Method of fabricating lower electrode of capacitor.
  10. Liu Chung-Shi,TWX, Method of preparing CU interconnect lines.
  11. Gupta Subhash,SGX ; Ho Kwok Keung Paul,SGX ; Zhou Mei-Sheng,SGX ; Chool Simon,SGX, Method to avoid copper contamination on the sidewall of a via or a dual damascene structure.
  12. Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.
  13. Kong-Beng Thei TW; Kuei-Ying Lee TW; Dun-Nian Yaung TW; Shou-Gwo Wuu TW, Method to reduce defects in shallow trench isolations by post liner anneal.
  14. Simon Andrew H. ; Uzoh Cyprian E., Open-bottomed via liner structure and method for fabricating same.
  15. Konecni Anthony J. ; Russell Noel, PVD deposition process for CVD aluminum liner processing.
  16. Patricia B. Smith ; Antonio L. P. Rotondaro, Plasma process for organic residue removal from copper.
  17. Koyama Kazuhide,JPX, Process for fabricating interconnection of semiconductor device.
  18. Wills Kendall S. (Houston TX), Process for making contacts and interconnects for holes having vertical sidewalls.
  19. Takenaka Nobuyuki,JPX, Process for producing a semiconductor device.
  20. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  21. Avanzino Steven ; Erb Darrell ; Cheung Robin ; Klein Rich, Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certa.
  22. Dalal Hormazdyar M. (Milton NY) Hutchings Kevin J. (Middletown NY) Rathore Hazara S. (Stormville NY), Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines.

이 특허를 인용한 특허 (40)

  1. Spinner, III,Charles R.; Nickell,Rebecca A.; Gandy,Todd H., Barrier film deposition over metal for reduction in metal dishing after CMP.
  2. Yang, Chih-Chao; Nitta, Satya V., Bilayer metal capping layer for interconnect applications.
  3. Clevenger, Lawrence A.; Li, Baozhen; Liu, Xiao H.; Peterson, Kirk D., Enhancement of iso-via reliability.
  4. Eshun, Ebenezer E.; Voldman, Steven H., High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballastin.
  5. Eshun,Ebenezer E.; Voldman,Steven H., High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature.
  6. Greco, Stephen E.; Topaloglu, Rasit O., Interconnect level structures for confining stitch-induced via structures.
  7. Greco, Stephen E.; Topaloglu, Rasit O., Interconnect level structures for confining stitch-induced via structures.
  8. Yang, Chih-Chao; Spooner, Terry A.; van der Straten, Oscar, Interconnect structure containing non-damaged dielectric and a via gouging feature.
  9. Kim, Sung-Bong; Kim, Joo-Young; Lim, Min-hwan, Method for manufacturing semiconductor device for suppressing detachment of conductive layer.
  10. Spinner, III, Charles R.; Nickell, Rebecca A.; Gandy, Todd H., Method for reduction in metal dishing after CMP.
  11. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  12. Ono, Hitohisa, Semiconductor device and method of manufacturing the same.
  13. Kim, Sung-Bong; Kim, Joo-Young; Lim, Min-hwan, Semiconductor device for suppressing detachment of conductive layer.
  14. Clevenger, Lawrence A.; Li, Baozhen; Peterson, Kirk D.; Spooner, Terry A.; Wang, Junli, Semiconductor via structure with lower electrical resistance.
  15. Peng, Tai-Yen; Wu, Chia-Tien; Cheng, Jye-Yen, Structure and formation method of damascene structure.
  16. Peng, Tai-Yen; Wu, Chia-Tien; Cheng, Jye-Yen, Structure and formation method of damascene structure.
  17. Yang, Chih-Chao; Horak, David Vaclav; Nogami, Takeshi; Ponoth, Shom, Structure and method for back end of the line integration.
  18. Yang, Chih Chao; Spooner, Terry A.; van der Straten, Oscar, Structure and method for metal integration.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  40. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로