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Voltage generating circuit and reference voltage source circuit employing field effect transistors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-003/16
출원번호 US-0748190 (2000-12-27)
우선권정보 JP-0372432 (1999-12-28); JP-0014330 (2000-01-24); JP-0386059 (2000-12-19)
발명자 / 주소
  • Shunsuke Andoh JP
  • Hirofumi Watanabe JP
출원인 / 주소
  • Ricoh Company, Ltd. JP
대리인 / 주소
    Dickstein Shapiro Morin & Oshinsky LLP
인용정보 피인용 횟수 : 75  인용 특허 : 5

초록

A voltage generating circuit includes a plurality of field effect transistors at least partially having gates same in conductivity type but different in impurity concentration. The gates are different in impurity concentration by not less than one digit.

대표청구항

1. A voltage generating circuit comprising a plurality of field effect transistors at least partially having gates same in conductivity type but different in impurity concentration.

이 특허에 인용된 특허 (5)

  1. Furutani Kiyohiro (Hyogo JPX), Intermediate potential generator stably providing an internal voltage precisely held at a predeterminded intermediate po.
  2. Yoh Kanji (Kokubunji JPX) Yamashiro Osamu (Omiya JPX) Meguro Satoshi (Kodaira JPX) Nagasawa Koichi (Kunitachi JPX) Nishimura Kotaro (Kokubunji JPX) Wakimoto Harumi (Hino JPX) Narita Kazutaka (Kodaira, Reference voltage generator device.
  3. Oguey Henri (Corcelles CHX) Gerber Bernard (Neuchatel CHX), Reference voltage source.
  4. Matsuura Yoshiaki (Tokyo JPX), Semiconductor device.
  5. Nishino Toshikazu (Kawasaki JPX) Miyake Mutsuko (Urawa JPX) Kawabe Ushio (Nishitama JPX) Harada Yutaka (Kodaira JPX) Aoki Masaaki (Minato JPX) Hirano Mikio (Ome JPX), Superconducting device.

이 특허를 인용한 특허 (75)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Aota,Hideyuki, Constant current generating circuit using resistor formed of metal thin film.
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  5. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Nomura, Hiroshi; Saiki, Takashi; Sakoda, Tsunehisa, Field effect transistors with different gate widths.
  16. Yoneda, Kazuhiro; Watanabe, Hirofumi; Negoro, Takaaki; Aisu, Katsuhiko; Nakatani, Yasukazu; Sakurano, Katsuyuki, Imaging device, control method of imaging device, and pixel structure.
  17. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  20. Lin,Yung Lin; Liu,Da, Liquid crystal display system with lamp feedback.
  21. Gheorghe, Ionel; Balteanu, Florinel G., Low power bandgap circuit.
  22. Coimbra, Ricardo Pureza; Vilas Boas, André Luis; Olmos, Alfredo, Low power circuit for amplifying a voltage without using resistors.
  23. Kobayashi, Daisuke, Low power input buffer using flipped gate MOS.
  24. Anderson, Brent A.; Nowak, Edward J., Metal-gate high-k reference structure.
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  26. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  27. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  28. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  29. Rios, Rafael; Doyle, Brian S.; Linton, Jr., Thomas D.; Kavalieros, Jack, N-gate transistor.
  30. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  31. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  32. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  33. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  38. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  39. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  40. Kinugawa,Hiroki; Ishikawa,Yoshinori, Output circuit.
  41. Negoro, Takaaki; Miki, Yoshihiko; Sakurano, Katsuyuki; Tsuda, Keiji; Watanabe, Hirofumi, Phototransistor and semiconductor device.
  42. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  43. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  44. Aota, Hideyuki, Reference voltage generation circuit, and constant voltage circuit using the reference voltage generation circuit.
  45. Wang, Zhenhua, Reference voltage generator providing a temperature-compensated output voltage.
  46. Watanabe, Hirofumi, Reference voltage source circuit operating with low voltage.
  47. Itoh,Kohzoh, Selecting a reference voltage suitable to load functionality.
  48. Kimura, Hajime, Semiconductor device.
  49. Kimura, Hajime, Semiconductor device.
  50. Kimura, Hajime, Semiconductor device.
  51. Kimura, Hajime, Semiconductor device.
  52. Kimura, Hajime, Semiconductor device.
  53. Kimura,Hajime, Semiconductor device.
  54. Kimura,Hajime, Semiconductor device including a pixel having current-driven light emitting element.
  55. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  56. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  57. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  58. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  59. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  60. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  61. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  62. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  63. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  64. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  65. Watanabe, Hirofumi, Temperature sensing circuit.
  66. Watanabe,Hirofumi, Temperature sensing circuit.
  67. Aota, Hideyuki; Watanabe, Hirofumi, Temperature sensor.
  68. Aota,Hideyuki; Watanabe,Hirofumi, Temperature sensor.
  69. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  70. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  71. Andoh, Shunsuke; Watanabe, Hirofumi, Voltage generating circuit and reference voltage source circuit employing field effect transistors.
  72. Andoh, Shunsuke; Watanabe, Hirofumi, Voltage generating circuit and reference voltage source circuit employing field effect transistors.
  73. Mitchell, David J.; Fraley, John R.; Yang, Jie; Schillig, Cora; Western, Bryon; Schupbach, Roberto Marcelo, Voltage regulator circuitry operable in a high temperature environment of a turbine engine.
  74. Dix, Gregory, Work function based voltage reference.
  75. Dix, Gregory, Work function based voltage reference.
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