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Substrate for electronic packaging, pin jig fixture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
  • H01R-012/04
출원번호 US-0424179 (2000-06-22)
우선권정보 IL-0120866 (1997-05-20)
국제출원번호 PCT/IL98/00230 (1999-05-20)
§371/§102 date 20000622 (20000622)
국제공개번호 WO98/53499 (1998-11-26)
발명자 / 주소
  • Shimon Neftin IL
  • Uri Mirsky IL
출원인 / 주소
  • Micro Components Ltd. IL
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 75  인용 특허 : 20

초록

A substrate for electronic packaging, the substrate having a discrete, generally prismatoid, initially electrically conductive valve metal solid body with one or more spaced apart, original valve metal vias each individually electrically islolated by a porous oxidized body portion therearound. A pin

대표청구항

1. A substrate for use in electronic packaging, the substrate consisting of a discrete, non-layered, solid body having a pair of generally parallel major surfaces and having one or more electrically insulated original valve metal vias substantially perpendicularly disposed to said major surfaces and

이 특허에 인용된 특허 (20)

  1. Parthasarathi Arvind ; Jalota Satish ; Schlater Jeffrey ; Strauman Lynn ; Braden Jeffrey S., Aluminum alloys for electronic components.
  2. Yoshida Yoshihiro (Atsugi JPX), Anisotropic conductive film.
  3. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.
  4. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Shepherd William H. ; Xie John Y. ; Jiang Hang, Ball grid array structure and method for packaging an integrated circuit chip.
  5. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Ball grid array with via interconnection.
  6. Yamakawa Akira (Hyogo JPX) Osada Mitsuo (Hyogo JPX) Ogasa Nobuo (Hyogo JPX), Ceramic circuit board and a method of manufacturing the ceramic circuit board.
  7. Yano Keiichi,JPX ; Asai Hironori,JPX, Heat transfer configuration for a semiconductor device.
  8. Larson Ralph I., High-terminal conductivity circuit board.
  9. Rabiet Jacques (Goncelin FRX) Gimenez Philippe (Echirolles FRX) Guillou Rmi (Nantes FRX) Drapier Claude (Vaucresson FRX), Insulated metal substrates and process for the production thereof.
  10. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
  11. Le Rouzic Jean (23 ; rue de Bourgogne 22300 Lannion FRX) Demeure Loic (Route de Pleumeur 22700 Perros-Guirec FRX) Le Roux Yvon (Le Rhu-Servel 22300 Lannion FRX), Metal support for an electronic component interconnection network and process for manufacturing this support.
  12. Hurwitz Dror,ILX ; Igner Eva,ILX ; Yofis Boris,ILX ; Katz Dror,ILX, Method for manufacturing an electronic structure.
  13. Ishii Tetsuro (Kagawa JPX) Oyama Tadanori (Kagawa JPX) Yamashita Masashi (Kagawa JPX) Kzome Kazuyuki (Kagawa JPX) Ikeda Tsutomu (Kagawa JPX) Fujioka Satoru (Kagawa JPX), Method of forming colored pattern on the surface of aluminum or aluminum alloy.
  14. Neftin Shimon (Kiriat Shmona ILX), Method of manufacturing a composite structure for use in electronic devices and structure, manufactured by said method.
  15. Kinard John T. ; Melody Brian J. ; Wheeler David A., Method of operating process for anodizing valve metals.
  16. Gibbs Stephen R. (Escondido CA) Chow Kuen (Del Mar CA), Multilevel metallization process.
  17. Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Pad array carrier IC device using flexible tape.
  18. Rll Rudolf (Marktredwitz DEX) Brandenburger Jrgen (Selb DEX) Hempel Horst (Marktredwitz DEX), Process and jig for plating pin grid arrays.
  19. Labunov Vladimir A. (Minsk BYX) Sokol Vitaly A. (Minsk BYX) Parkun Vladimir M. (Minsk BYX) Vorob\yova Alla I. (Minsk BYX), Process for making multilevel interconnections of electronic components.
  20. Horiuchi Michio,JPX ; Kazama Takuya,JPX, Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate.

이 특허를 인용한 특허 (75)

  1. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.
  2. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.
  3. St. Amand, Roger D., Column and stacking balls package fabrication method and structure.
  4. Haba,Belgacem; Beroz,Masud; Tuckerman,David B.; Humpston,Giles; Crisp,Richard Dewitt, Connection structures for microelectronic devices and methods for forming such structures.
  5. Sutardja, Sehat, Efficient transistor structure.
  6. Sutardja, Sehat, Efficient transistor structure.
  7. Sutardja, Sehat, Efficient transistor structure.
  8. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.
  9. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.
  10. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Encapsulated semiconductor package.
  11. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  12. Bolognia, David; Adlam, Ted; Kelly, Mike, Fingerprint sensor package and method.
  13. Darveaux, Robert Francis; Bancod, Ludovico E.; Mattei, Marnie Ann; Olson, Timothy Lee, Flex circuit package and method.
  14. Pasternak, Eliezer; Cahill, Sean; Hom, Bance, High frequency device packages and methods.
  15. Sutardja, Sehat, Integrated circuits and interconnect structure for integrated circuits.
  16. Sutardja, Sehat, Integrated circuits and interconnect structure for integrated circuits.
  17. Sutardja, Sehat, Integrated circuits and interconnect structure for integrated circuits.
  18. Sutardja,Sehat, Integrated circuits and interconnect structure for integrated circuits.
  19. Sutardja,Sehat, Interconnect structure for power transistors.
  20. Lee, DongHoon; Kim, DoHyung; Park, JungSoo; Han, SeungChul; Kim, JooHyun; Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package.
  21. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Bolognia, David, Light emitting diode (LED) package and method.
  22. Sanjuan, Eric A.; Cahill, Sean S., Low cost high frequency device package and methods.
  23. Sanjuan, Eric A.; Cahill, Sean S., Low cost high frequency device package and methods.
  24. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package.
  25. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package and method.
  26. Uzoh, Cyprian Emeka; Arkalgud, Sitaram, Method for preparing low cost substrates.
  27. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  28. Sanjuan, Eric A.; Cahill, Sean S., Method of making a high frequency device package.
  29. Nicholls, Louis W.; St. Amand, Roger D.; Kim, Jin Seong; Jung, Woon Kab; Yang, Sung Jin; Darveaux, Robert F., Methods and structures for increasing the allowable die size in TMV packages.
  30. Haba, Belgacem; Beroz, Masud; Tuckerman, David B.; Humpston, Giles; Crisp, Richard Dewitt, Methods for forming connection structures for microelectronic devices.
  31. Dreiza, Mahmoud; Ballantine, Andrew; Shumway, Russell Scott, Molded cavity substrate MEMS package fabrication method and structure.
  32. Pasternak, Eliezer; Cahill, Sean; Hom, Bance, Process of manufacturing high frequency device packages.
  33. Kim, Do Hyung; Kang, Dae Byoung; Han, Seung Chul, Semiconductor device.
  34. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Ahn, Ye Sul, Semiconductor device and fabricating method thereof.
  35. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  36. Clark, David; Zwenger, Curtis, Semiconductor device and manufacturing method thereof.
  37. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.
  38. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.
  39. Ryu, Ji Yeon; Kim, Byong Jin; Shim, Jae Beum, Semiconductor device and manufacturing method thereof.
  40. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  41. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  42. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  43. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  44. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  45. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  46. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  47. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  48. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  49. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  50. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  51. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  52. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  53. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  54. Bancod, Ludovico E.; Kim, Jin Seong; Wachtler, Kurt Peter, Stackable plasma cleaned via package and method.
  55. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable protruding via package and method.
  56. Darveaux, Robert Francis; Bancod, Ludovico; Yoshida, Akito, Stackable treated via package and method.
  57. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  58. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  59. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  60. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  61. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  62. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  63. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  64. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  65. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Troche, Jr., Louis B.; Syed, Ahmer; Shumway, Russell, Stacked and staggered die MEMS package and method.
  66. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  67. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  68. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  69. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  70. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  71. He, Runsheng; Qian, Haoli, Transmitter digital-to-analog converter with noise shaping.
  72. He,Runsheng; Qian,Haoli, Transmitter digital-to-analog converter with noise shaping.
  73. St. Amand, Roger D., Underfill contacting stacking balls package fabrication method and structure.
  74. Jung, Boo Yang; Paek, Jong Sik; Lee, Choon Heung; Park, In Bae; Kim, Sang Won; Kim, Sung Kyu; Lee, Sang Gyu, Wafer level fan out semiconductor device and manufacturing method thereof.
  75. Nakai, Toru; Chen, Liyi, Wiring substrate and method for manufacturing wiring substrate.
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