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Semiconductor device having a low dielectric layer as an interlayer insulating layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-051/40
  • H01L-023/485
  • H01L-029/40
  • H01L-029/06
출원번호 US-0192335 (1998-11-16)
우선권정보 JP-0315682 (1997-11-17); JP-0037673 (1998-02-19); JP-0109983 (1998-04-20)
발명자 / 주소
  • Toshiaki Hasegawa JP
  • Hajime Nakayama JP
출원인 / 주소
  • Sony Corporation JP
대리인 / 주소
    Rader, Fishman & Grauer PLLC
인용정보 피인용 횟수 : 43  인용 특허 : 18

초록 ▼

A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in contact with the insulating layer in the dielectri

대표청구항 ▼

1. A semiconductor device comprising:a semiconductor substrate; an insulating layer formed on the substrate; a first dielectric layer formed on the insulating layer and having a dielectric constant of not more than 3.0; and an interconnection layer formed in the first dielectric layer and contacting

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  4. Jeng Shin-Puu ; Chang Mi-Chang, Highly thermally conductive interconnect structure for intergrated circuits.
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  5. Lu Jiong-Ping ; Jin Changming, Integrated circuit dielectric and method.
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  6. Cave Nigel G. ; Yu Kathleen C. ; Farkas Janos, Integrated circuit having a support structure.
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  7. Jeng Shin-Puu, Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials.
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  8. Jeng Shin-Puu ; Taylor Kelly J., Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials.
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  9. Weigand Peter,DEX ; Tobben Dirk, Metalization system having an enhanced thermal conductivity.
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  10. Chen Lai-Juh,TWX ; Wang Chien-Mei,TWX, Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant pol.
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  11. Hong Qi-Zhong ; Hsu Wei-Yung ; Lu Jiong-Ping ; Havemann Robert H., Method of forming diffusion barriers for copper metallization in integrated cirucits.
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  12. Gnade Bruce E. ; Cho Chih-Chen ; Smith Douglas M., Method of making a low dielectric constant material for electronics.
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  13. Havemann Robert H. ; Jeng Shin-puu, Multilevel interconnect structure with air gaps formed between metal leads.
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  14. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
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  15. Watanabe Joy Kimi ; Stankus John Joseph, Process for forming a semiconductor device.
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  16. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
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  17. Tsui Ting Y. ; Adem Ercan, Semiconductor device having a low dielectric constant material.
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  18. Hayashi Yoshihiro,JPX ; Onodera Takahiro,JPX, Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance.
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