$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Selective cap layers over recessed polysilicon plugs 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0632830 (2000-08-07)
발명자 / 주소
  • Allen McTeer
  • Steven T. Harshfield
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Knobbe, Martens, Olson & Bear, LLP
인용정보 피인용 횟수 : 80  인용 특허 : 20

초록

Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical

대표청구항

1. A method of selectively forming a cap layer for a conductive plug of an integrated circuit, comprising:forming a via in an insulating layer, the via exposing a semiconductor substrate; forming a partial plug partially filling the via and directly contacting the substrate; depositing a sacrificial

이 특허에 인용된 특허 (20)

  1. Sandhu Gurtej S. (Boise ID) Fazan Pierre (Boise ID), Barrier layers for ferroelectric and pzt dielectric on silicon.
  2. Sandhu Gurtej S. (Boise ID) Fazan Pierre C. (Boise ID), Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for fo.
  3. Mihara Takashi (Iruma JPX) Yoshimori Hiroyuki (Fujino-machi JPX) Watanabe Hitoshi (Tokyo JPX) McMillan Larry D. (Colorado Springs CO) De Araujo Carlos P. (Colorado Springs CO), Ferroelectric integrated circuit.
  4. Anand Kranti V. (late of Sunnyvale CA by Madhu Anand ; sole heir) Thomas Michael E. (Milpitas CA), High value tantalum oxide capacitor.
  5. Byun Jeong Soo (Chungcheongbuk-do KRX), Method for forming platinum silicide plugs.
  6. Igarashi Yasushi,JPX, Method for manufacturing semiconductor memory device.
  7. Sameshima Katsumi (Kyoto JPX), Method for producing a semiconductor device having a ferroelectric storage cell.
  8. Summerfelt Scott R. (Dallas TX), Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes.
  9. Ogure Naoaki,JPX ; Inoue Hiroaki,JPX, Method of forming embedded copper interconnections and embedded copper interconnection structure.
  10. Fukuyama Toshiaki (Nara JPX) Matoba Masakazu (Tenri JPX) Ishimoto Yoshihisa (Sakai JPX) Kishida Masahiro (Nabari JPX) Yoshimizu Toshiyuki (Soraku-gun JPX) Seike Takeshi (Kitakatsuragi-gun JPX), Method of making two-terminal nonlinear device and liquid crystal apparatus including the same.
  11. Toure Abron S. (Stoughton MA) Collins Steven R. (Lexington MA) LeBlanc Bruce W. (Manchester NH), Method of manufacturing a ferroelectric device using a plasma etching process.
  12. Yoon Euisik (Sunnyvale CA) Kovacs Ronald P. (Mountain View CA) Thomas Michael E. (Milpitas CA), Method of providing a dielectric structure for semiconductor devices.
  13. Chan Lap ; Li Sam Fong Yau,SGX ; Ng Hou Tee,SGX, Method to encapsulate copper plug for interconnect metallization.
  14. Takenaka Kazuhiro (Suwa JPX), Platinum capacitor MOS memory having lattice matched PZT.
  15. Azuma Masamichi (Colorado Springs CO) Scott Michael C. (Colorado Springs CO) Paz de Araujo Carlos A. (Colorado Springs CO) McMillan Larry D. (Colorado Springs CO), Process for making metal oxides.
  16. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  17. Kato Koji (Suwa JPX), Semiconductor device having a ferroelectric film in a through-hole.
  18. Takenaka Kazuhiro (Suwa JPX), Semiconductor device with ferroelectric and method of manufacturing the same.
  19. Momose Hisayo S. (Tokyo JPX), Semiconductor memory device having a ferroelectric substance as a memory element.
  20. Emesh Ismail T. (Cumberland CAX) Calder Iain D. (Kanata CAX) Ho Vu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Madsen Lynnette D. (Ottawa CAX), Structure and method of making a capacitor for an intergrated circuit.

이 특허를 인용한 특허 (80)

  1. Pacetti, Stephen Dirk; DesNoyer, Jessica; Chen, Yung Ming; Kleiner, Lothar; Hossainy, Syed F. A., Abluminal, multilayer coating constructs for drug-delivery stents.
  2. Pacetti, Stephen Dirk; DesNoyer, Jessica; Chen, Yung-Ming; Kleiner, Lothar; Hossainy, Syed F. A., Abluminal, multilayer coating constructs for drug-delivery stents.
  3. Chen, Yung Ming; Tang, Fuh Wei, Apparatus and method for electrostatic coating of an abluminal stent surface.
  4. Hu, Y. Jeff, Buried digit line stack and process for making same.
  5. Hu, Y. Jeff, Buried digit line stack and process for making same.
  6. Lee, Kong-Soo, Capacitor of an integrated circuit device and method of manufacturing the same.
  7. Lee, Kong-Soo, Capacitor of an integrated circuit device and method of manufacturing the same.
  8. Lee, Kong-Soo, Capacitor of an integrated circuit device and method of manufacturing the same.
  9. Lee,Kong Soo, Capacitor of an integrated circuit device and method of manufacturing the same.
  10. Fragola, Felice, Closure for containers, in particular plug for bottles.
  11. Sitaram, Arkalgud; Dehm, Christine; Mazur?-Espejo, Carlos, Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure.
  12. Wang, Yun; Chiang, Tony P.; Hashim, Imran, Current-limiting layer and a current-reducing layer in a memory device.
  13. Wang, Yun; Chiang, Tony; Hashim, Imran, Defect gradient to boost nonvolatile memory performance.
  14. Wang, Yun; Chiang, Tony; Hashim, Imran, Defect gradient to boost nonvolatile memory performance.
  15. Li, Dong, Deposition of ruthenium or ruthenium dioxide.
  16. Bandyopadhyay, Abhijit; Kumar, Tanmay; Herner, Scott Brad; Petti, Christopher J.; Scheuerlein, Roy E., Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same.
  17. Pore, Viljami J.; Haukka, Suvi P.; Blomberg, Tom E.; Tois, Eva E., Doped metal germanide and methods for making the same.
  18. Elkins, Patricia C.; Moore, John T.; Klein, Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  19. Elkins,Patricia C.; Moore,John T.; Klein,Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  20. Haukka, Suvi P.; Tuominen, Marko J.; Rahtu, Antti, Enhanced deposition of noble metals.
  21. Haukka, Suvi P.; Tuominen, Marko J.; Rahtu, Antti, Enhanced deposition of noble metals.
  22. Haukka, Suvi P.; Tuominen, Marko J.; Rahtu, Antti, Enhanced deposition of noble metals.
  23. McDaniel,Terrence, Low resistance peripheral contacts while maintaining DRAM array integrity.
  24. Tuttle,Mark E., Magneto-resistive memory and method of manufacturing the same.
  25. Cleeves,James M., Memory cell with high-K antifuse for reverse bias programming.
  26. Pore, Viljami J.; Haukka, Suvi P.; Blomberg, Tom E.; Tois, Eva E., Metal silicide, metal germanide, methods for making the same.
  27. Pore, Viljami J.; Haukka, Suvi P.; Blomberg, Tom E.; Tois, Eva E., Metal silicide, metal germanide, methods for making the same.
  28. Hartner, Walter; Weinrich, Volker; Kronke, Matthias, Method for fabricating a capacitor configuration.
  29. Lee, Yoon Jik; Kim, Jeong Tae, Method for fabricating cell plugs of semiconductor device.
  30. Shinriki, Hiroshi; Jeong, Daekyun, Method for forming Ta-Ru liner layer for Cu wiring.
  31. Liu, Ai-Sen; Perng, Baw-Ching; Lei, Ming-Ta; Wan, Wen-Kai; Lin, Cheng-Chung; Huang, Kuei-Wu; Lin, Yih-Shung; Lin, Chia-Hui, Method for forming a semiconductor device having high-K gate dielectric material.
  32. Shinriki, Hiroshi; Namba, Kunitoshi; Jeong, Daekyun, Method for forming metal film by ALD using beta-diketone metal complex.
  33. Fox, Jason; Harold, Nathan; Templin, Barry; Tochterman, Andrew, Method for selectively coating surfaces of a stent.
  34. Higashitani, Masaaki, Method of forming low resistance void-free contacts.
  35. Kostamo, Juhana; Soininen, Pekka J.; Elers, Kai-Erik; Haukka, Suvi, Method of growing electrical conductors.
  36. Park,Shin Seung, Method of manufacturing semiconductor device.
  37. Yan,John Y.; Chan,Randy, Method of reducing or eliminating thrombus formation.
  38. Pore, Viljami J.; Haukka, Suvi P.; Blomberg, Tom E.; Tois, Eva E., Methods for depositing nickel films and for making nickel silicide and nickel germanide.
  39. Kim, Jong Su; Park, Hyung Sang, Methods of depositing a ruthenium film.
  40. Raghu, Prashant, Methods of forming capacitors.
  41. Woodruff, Jacob Huffman, Methods of forming metal silicides.
  42. Woodruff, Jacob Huffman, Methods of forming metal silicides.
  43. Raghu, Prashant, Methods of forming semiconductor constructions.
  44. Raghu, Prashant, Methods of forming semiconductor constructions.
  45. Craig, Charles H.; Papp, John E.; Jayasinghe, Dudley; Hines, Lionel G.; Orosa, Dennis, Nanobead releasing medical devices.
  46. Ludwig, Florian N., Nanoshell therapy.
  47. Ludwig, Florian Niklas, Nanoshell therapy.
  48. Ludwig, Florian N.; Pacetti, Stephen D.; Hossainy, Syed F. A.; Davalian, Dariush, Nanoshells for drug delivery.
  49. Ludwig, Florian Niklas; Pacetti, Stephen D.; Hossainy, Syed F. A.; Davalian, Dariush, Nanoshells on polymers.
  50. Ludwig, Florian Niklas; Pacetti, Stephen D.; Hossainy, Syed F. A.; Davalian, Dariush, Nanoshells on polymers.
  51. Ludwig, Florian Niklas; Pacetti, Stephen D.; Hossainy, Syed F. A.; Davalian, Dariush, Nanoshells on polymers.
  52. Tendulkar, Mihir; Hashim, Imran; Wang, Yun, Nonvolatile memory device using a tunnel oxide as a current limiter element.
  53. Tendulkar, Mihir; Hashim, Imran; Wang, Yun, Nonvolatile memory device using a tunnel oxide as a passive current steering element.
  54. Tendulkar, Mihir; Hashim, Imran; Wang, Yun, Nonvolatile memory device using a varistor as a current limiter element.
  55. Tendulkar, Mihir; Hashim, Imran; Wang, Yun, Nonvolatile memory device using a varistor as a current limiter element.
  56. Chen, Charlene; Pramanik, Dipankar, Nonvolatile resistive memory element with a passivated switching layer.
  57. Bunyk, Paul I, RSFQ Batcher-banyan switching network.
  58. Lian, Jingyu; Costrini, Greg; Economikos, Laertis; Wise, Michael, Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure.
  59. Van Sciver, Jason, Rotatable support elements for stents.
  60. Van Sciver, Jason, Rotatable support elements for stents.
  61. Van Sciver, Jason, Rotatable support elements for stents.
  62. Van Sciver, Jason, Rotatable support elements for stents.
  63. Van Sciver, Jason, Rotatable support elements for stents.
  64. Shinriki, Hiroshi; Inoue, Hiroaki, Ruthenium alloy film for copper interconnects.
  65. Hossainy,Syed F. A.; Mirzaee,Daryush, Selective coating of medical devices.
  66. Huotari, Hannu; Tuominen, Marko; Leinikka, Miika, Selective deposition of noble metal thin films.
  67. Huotari, Hannu; Tuominen, Marko; Leinikka, Miika, Selective deposition of noble metal thin films.
  68. Huotari, Hannu; Tuominen, Marko; Leinikka, Miika, Selective deposition of noble metal thin films.
  69. Huotari, Hannu; Tuominen, Marko; Leinikka, Miika, Selective deposition of noble metal thin films.
  70. Kilpelä,Olli V.; Koh,Wonyong; Huotari,Hannu A.; Tuominen,Marko; Leinikka,Miika, Selective formation of metal layers in an integrated circuit.
  71. Tochterman, Andrew J.; Fox, William J.; Harold, Nathan, Selectively coating luminal surfaces of stents.
  72. Choi, Suk-hun; Bae, Ki-ho; Hong, Yi-koan; Kim, Kyung-hyun; Kim, Tae-hyun; Nam, Kyung-tae; Jeong, Jun-ho, Semiconductor device having a conductive structure including oxide and non oxide portions.
  73. Lee, Yoon Jik; Kim, Jeong Tae, Semiconductor device having cell plugs.
  74. Fox, Jason; Harold, Nathan; Templin, Barry; Tochterman, Andrew, Stent mandrel fixture and method for selectively coating surfaces of a stent.
  75. Fox,Jason; Harold,Nathan; Templin,Barry; Tochterman,Andrew, Stent mandrel fixture and method for selectively coating surfaces of a stent.
  76. Pacetti,Stephen D.; Villareal,Plaridel K., Stent mounting assembly and a method of using the same to coat a stent.
  77. Chen, Yung Ming; Ho, Henjen, System and method for coating an implantable medical device.
  78. McTeer, Allen, System and method for sputtering a tensile silicon nitride film.
  79. Kang, Shin-Jae; Oh, Gyuhwan; Park, Insun; Lim, Hyunseok; Lim, Nak-Hyun, Variable resistance non-volatile memory cells and methods of fabricating same.
  80. Chung, Dae Hyuk; Hwang, In Seak, Wiring structure of a semiconductor device and method of forming the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로