초록 ▼

An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the add

An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

대표청구항 ▼

1. A system for verifying addressing logic included in a storage device, wherein the storage device includes a plurality of addressable locations each for storing data signals, and wherein predetermined ones of the addressable locations stores, as ones of the data signals, address signals indicative

1. A system for verifying addressing logic included in a storage device, wherein the storage device includes a plurality of addressable locations each for storing data signals, and wherein predetermined ones of the addressable locations stores, as ones of the data signals, address signals indicative of the address for the respective one of the predetermined ones of the addressable locations, the system, comprising:read addressing means for providing a read address to the storage device to read a selectable one of the addressable locations within the storage device; and read address compare means coupled to said read addressing means for receiving said read address, for receiving the address signals from said selectable one of the addressable locations if said selectable one of the addressable locations is one of the predetermined ones of the addressable locations, and for generating a read address error indicator if said read address has a predetermined relationship to said address signals from said selectable one of the addressable locations.