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Transistor pattern for voltage regulator 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-001/40
  • H01L-023/053
출원번호 US-0892233 (2001-06-26)
발명자 / 주소
  • Andrew J. Burstein
  • Charles Nickel
출원인 / 주소
  • Volterra Semiconductor Corporation
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 56  인용 특허 : 5

초록

A voltage regulator with an input terminal and an output terminal has a printed circuit board, a substrate mounted on the printed circuit board, and a first flip-chip type integrated circuit chip mounted on the substrate. The first integrated circuit chip includes a first power switch fabricated the

대표청구항

1. An integrated circuit structure comprising:a substrate having a first plurality of doped regions and a second plurality of doped regions, the first plurality of doped regions and the second plurality of doped regions being arranged in an alternating pattern; and a gate region on the substrate sep

이 특허에 인용된 특허 (5)

  1. Hallberg Alan ; Nguyen Don J., Buck converter.
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  3. Burstein Andrew J. ; Nickel Charles, Flip-chip switching regulator.
  4. McMahon John Francis (Phoenix AZ), Kangaroo multi-package interconnection concept.
  5. Stager Mark P. ; Yee Abraham F. ; Padmanabhan Gobi R., Semiconductor chip package with interconnect layers and routing and testing methods.

이 특허를 인용한 특허 (56)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  2. Owyang, King; Kasem, Mohammed; Bai, Yuming; Kuo, Frank; Mao, Sen; Kuo, Sam, Complete power management system implemented in a single surface mount package.
  3. Owyang, King; Kasem, Mohammed; Bai, Yuming; Kuo, Frank; Mao, Sen; Kuo, Sam, Complete power management system implemented in a single surface mount package.
  4. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  5. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  6. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  7. Tang, Joel; Zhang, Qingxiang; Kahn, Seth; Lidsky, David, Controlled delivery of a charging current to a boost capacitor of a voltage regulator.
  8. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  9. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  10. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  11. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  12. Polhemus, Gary D.; Carroll, Robert T.; Desbiens, Donald J., Electrical connectivity for circuit applications.
  13. Carroll, Robert T., Electrical connectivity of die to a host substrate.
  14. Carroll, Robert T., Electrical connectivity of die to a host substrate.
  15. Tang, Joel; Yeoh, Charles; Kahn, Seth; Lidsky, David; McJimsey, Michael, Feedback for controlling the switching frequency of a voltage regulator.
  16. Stone, Marshall David, Integrated circuit driver having stable bootstrap power supply.
  17. Nickel, Charles; Nickel, legal representative, Katherine; Lidsky, David; Kahn, Seth, Integrated electrical circuit and test to determine the integrity of a silicon die.
  18. Jergovic, Ilija; Yao, Kaiwei; Stratakos, Anthony J., Integrated photovoltaic panel with sectional maximum power point tracking.
  19. Zhong, Guo Hua; Yang, Mei, Layout and pad floor plan of power transistor for good performance of SPU and STOG.
  20. Hori, Toshiyuki, Method for manufacturing a semiconductor wiring base that includes a wiring base with wiring extending inside and outside of a mounting region.
  21. Deboy, Gerald; Leong, Kennith Kin, Method for operating a power converter circuit and power converter circuit.
  22. Deboy, Gerald; Leong, Kennith Kin, Method for operating a power converter circuit and power converter circuit.
  23. Cho, Eung San; Fernando, Dean; Philips, Tim; Clavette, Dan, Monolithic power converter package.
  24. Eden, Richard C.; Smetana, Bruce A., POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS, INTEGRATED CIRCUIT ASSEMBLIES, INTEGRATED CIRCUITRY, POWER CURRENT SWITCHING METHODS, METHODS OF FORMING A POWER SEMICONDUCTOR SWITCHING DEVIC.
  25. Eden, Richard C.; Smetana, Bruce A., POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS, INTEGRATED CIRCUIT ASSEMBLIES, INTEGRATED CIRCUITRY, POWER CURRENT SWITCHING METHODS, METHODS OF FORMING A POWER SEMICONDUCTOR SWITCHING DEVIC.
  26. Deboy, Gerald; Krischan, Klaus; Weis, Rolf, Power converter circuit.
  27. Eden,Richard C.; Smetana,Bruce A., Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching devic.
  28. Saito, Hiroshi; Wada, Ryo; Goto, Yuichi, Semiconductor device and DC-to-DC converter.
  29. Ishida,Kaoru, Semiconductor device and electronic equipment using the same.
  30. Lotfi, Ashraf W.; Demski, Jeffrey; Feygenson, Anatoly; Lopata, Douglas Dean; Norton, Jay; Weld, John D., Semiconductor device including a redistribution layer and metallic pillars coupled thereto.
  31. Lotfi, Ashraf W.; Demski, Jeffrey; Feygenson, Anatoly; Lopata, Douglas Dean; Norton, Jay; Weld, John D., Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips.
  32. Lotfi, Ashraf W.; Demski, Jeffrey; Feygenson, Anatoly; Lopata, Douglas Dean; Norton, Jay; Weld, John D., Semiconductor device including gate drivers around a periphery thereof.
  33. Osburn,Edward P., Semiconductor device power interconnect striping.
  34. Nemtsev, Gennadiy; Wang, Hui; Zheng, Yingping; Nair, Rajesh, Semiconductor power device having a diamond shaped metal interconnect scheme.
  35. Tournatory, David Christian Gerard; Kahn, Seth, Sensing and feedback in a current mode control voltage regulator.
  36. Kahn, Seth, Sensing and feedback with enhanced stability in a current mode control voltage regulator.
  37. Sandner, Christoph; Riederer, Roman; Höglauer, Josef; Auer, Stephan, Switched-mode power converter with split partitioning.
  38. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  39. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  40. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  41. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  42. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  43. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  44. Stratakos, Anthony J.; McJimsey, Michael D.; Jergovic, Ilija; Ikriannikov, Alexandr; Der Minassians, Artin; Yao, Kaiwei; Lidsky, David B.; Zuniga, Marco A.; Borisavljevic, Ana, Switching circuits for extracting power from an electric power source and associated methods.
  45. Ikriannikov, Alexandr; Stratakos, Anthony J., System, method, module, and energy exchanger for optimizing output of series-connected photovoltaic and electrochemical devices.
  46. Burstein, Andrew; Chakraborty, Sombuddha; Xiong, Yali; McJimsey, Michael D.; Roessig, Trey A.; Panseri, Luigi; Choi, Paul H.; Burmas, Theodore V.; Beronja, Biljana; Garcea, Giovanni; Jergovic, Ilija; Pizzutelli, Andrea; Stratakos, Anthony J., Systems and methods for DC-to-DC converter control.
  47. Burstein, Andrew; Chakraborty, Sombuddha; Xiong, Yali; McJimsey, Michael D.; Roessig, Trey A.; Panseri, Luigi; Choi, Paul H.; Burmas, Theodore V.; Beronja, Biljana; Garcea, Giovanni; Jergovic, Ilija; Pizzutelli, Andrea; Stratakos, Anthony J., Systems and methods for DC-to-DC converter control.
  48. Chakraborty, Sombuddha; Xiong, Yali; McJimsey, Michael D.; Stratakos, Anthony J.; Garcea, Giovanni; Jergovic, Ilija; Burstein, Andrew; Pizzutelli, Andrea, Systems and methods for DC-to-DC converter control.
  49. Chakraborty, Sombuddha; Xiong, Yali; McJimsey, Michael D.; Stratakos, Anthony J.; Garcea, Giovanni; Jergovic, Ilija; Burstein, Andrew; Pizzutelli, Andrea, Systems and methods for DC-to-DC converter control.
  50. McJimsey, Michael D.; Lidsky, David B.; Burstein, Andrew; Garcea, Giovanni; Flasck, Jeremy M.; Jergovic, Ilija; Pizzutelli, Andrea, Systems and methods for DC-to-DC converter control.
  51. McJimsey, Michael D.; Lidsky, David B.; Burstein, Andrew; Garcea, Giovanni; Flasck, Jeremy M.; Jergovic, Ilija; Pizzutelli, Andrea, Systems and methods for DC-to-DC converter control.
  52. Kahn, Seth; Tang, Joel; Chen, Jingquan, Virtual output voltage sensing for feed-forward control of a voltage regulator.
  53. Suppanz, Bradley J.; Djekic, Ognjen, Voltage regulator control using information from a load.
  54. Lacap, Efren M.; Nariani, Subhash Rewachand; Nickel, Charles, Wafer-level chip scale package.
  55. Lacap, Efren M.; Nariani, Subhash Rewachand; Nickel, Charles, Wafer-level chip scale package.
  56. Hori,Toshiyuki, Wiring base with wiring extending inside and outside of a mounting region.
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