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Circuit and method for trimming integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/26
  • H01L-029/00
  • H03M-001/10
출원번호 US-0489660 (2000-01-24)
발명자 / 주소
  • You-Yuh Shyr
  • Sorin Laurentiu Negru
출원인 / 주소
  • Micro International Limited KY
대리인 / 주소
    Grossman, Tucker, Perreault & Pfleger, PLLC
인용정보 피인용 횟수 : 25  인용 특허 : 19

초록

A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a r

대표청구항

1. A programmable after-package, on-chip reference voltage trim circuit for an IC, said programmable trim circuit comprising: a register being controlled to generate a sequence of test bit signal and a sequence of set bit signals; a plurality of after package programmable trim cell circuits selectiv

이 특허에 인용된 특허 (19)

  1. Stolfa David L. (Phoenix AZ), Circuit and method of previewing analog trimming.
  2. Ueda Kenji (Ohtsu JPX), Circuit resistance adjusting device.
  3. Saitoh Yutaka (Tokyo JPX) Osanai Jun (Tokyo JPX) Kojima Yoshikazu (Tokyo JPX) Ishii Kazutoshi (Tokyo JPX), Current regulating semiconductor integrated circuit device and fabrication method of the same.
  4. de Wit Michiel (Dallas TX) Tan Khen-Sang (Singapore SGX), Differential fuse circuit and method utilized in an analog to digital converter.
  5. Connolly ; Jr. Joseph J. (San Jose CA) Redfern Thomas P. (San Jose CA) Frederiksen Thomas M. (San Jose CA), Digital error correcting trimming in an analog to digital converter.
  6. Petit Dominique A.,FRX, Electrically adjustable resistor structure.
  7. Smayling Michael C. (Missouri City TX) D\Arrigo Sebastiano (Houston TX) Imondi Giuliano (Rieti ITX) Vergara Sossio (Frattamaggiore ITX), Electrically programmable fuse circuit for an integrated-circuit chip.
  8. Shu Tzi-Hsiung ; Bacrania Kantilal, Integrated circuit analog-to-digital converter and associated calibration method and apparatus.
  9. Dobkin Robert C. (Hillsborough CA), Integrated circuit on chip trimming.
  10. Pease Robert A. (San Francisco CA), Integrated circuit trimming.
  11. Shieh Sui P. (Los Altos CA), Low power trim circuit and method.
  12. Nguyen Baoson (Plano TX), Method and apparatus for trimming an electrical value of a component of an integrated circuit.
  13. Nelson Carl T. (Sunnyvale CA), Multiple trim structure.
  14. Kajigaya Kazuhiko (Iruma JPX) Udagawa Tetsu (Iruma JPX) Ishii Kyoko (Tokyo JPX) Tsunozaki Manabu (Ohme JPX) Oshima Kazuyoshi (Ohme JPX) Horiguchi Masashi (Kawasaki JPX) Etoh Jun (Hachioji JPX) Aoki M, Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value comp.
  15. Uchiyama Akira (Kodaira JPX) Shibata Ryuji (Higashiyamato JPX) Nakagome Yoshinobu (Hamura JPX) Kubo Masaharu (Hachiouji JPX), Semiconductor integrated circuit device having an internally produced operation voltage matched to operation speed of ci.
  16. Nomura Yukihiro (Kawasaki JPX) Ito Shigemasa (Kasugai JPX), Semiconductor integrated circuit device having built-in step-down circuit for stepping down external power supply voltag.
  17. Akamatsu Hiroshi,JPX, Semiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail d.
  18. Price John J. (Mesa AZ), Trim network for monolithic circuits and use in trimming a d/a converter.
  19. Russell Ronald W. (Sunnyvale CA) Lambert Craig N. (San Jose CA), User-proof post-assembly offset voltage trim.

이 특허를 인용한 특허 (25)

  1. Bardsley, Scott Gregory; Dillon, Christopher, Analog to digital converter with bandwidth tuning circuit.
  2. Bardsley,Scott G.; Rigsbee,Baeton C., Calibration of analog to digital converter by means of multiplexed stages.
  3. Shyr, You-Yuh; Negru, Sorin Laurentiu, Circuit and method for trimming integrated circuits.
  4. Shyr,You Yuh; Negru,Sorin Laurentiu, Circuit and method for trimming integrated circuits.
  5. Spenea, Marian Udrea; Bucur, Constantin; Niculae, Marian; Simion, George; Marinescu, Viorel, Circuit and method for trimming locking of integrated circuits.
  6. Manganaro, Gabriele, Circuits for on-situ differential impedance balance error measurement and correction.
  7. Harmer,Brent Jay; Koay,KarWei, Detecting back electromotive force voltage.
  8. Naito, Kensaku, Device for analyzing failure in semiconductor device provided with internal voltage generating circuit.
  9. Wu, Shien-Yang, Electrical fuse element test structure and method.
  10. Cranford, Jr.,Hayden Clavie; Hsu,Louis Lu Chen; Mason,James Stephen; Nicholls,Gareth John; Murfet,Philip; Ray,Samuel, Electronic component value trimming systems.
  11. He, Zaisheng; Li, Moutao; Xiao, Lirong, Method and apparatus for adjusting and obtaining a reference voltage.
  12. Lorenz,Harald, Method and apparatus for calibration of an on-chip temperature sensor within a memory device.
  13. Abadeer,Wagdi W.; Appleyard,Jennifer E.; Fifield,John A.; Tonti,William R., Method and circuit for compensating for tunneling current.
  14. Gavrila,Gabe C.; Littlefield,Troy J.; Martin Lopez,Fernando Ramon, Method and circuits for performing offline circuit trimming.
  15. Luo, Ruei-Chin; Chou, Chung-Cheng; Wu, Ching-Wei, Multiple-time programmable electrical fuse utilizing MOS oxide breakdown.
  16. Bardsley, Scott Gregory, Pipeline ADC digital dithering for increased digital calibration resolution.
  17. Pirkle, Rex W.; Harbert, Curtis L.; Reeves, George, Selective trim and wafer testing of integrated circuits.
  18. Kohara,Koji, Semiconductor integrated circuit with fuse data read circuit.
  19. Rasbornig, Friedrich; Motz, Mario; Hammerschmidt, Dirk; Gastinger, Ferdinand; Schaffer, Bernhard; Granig, Wolfgang, Sensor self-diagnostics using multiple signal paths.
  20. Rasbornig, Friedrich; Motz, Mario; Hammerschmidt, Dirk; Gastinger, Ferdinand; Schaffer, Bernhard; Granig, Wolfgang, Sensor self-diagnostics using multiple signal paths.
  21. Rasbornig, Friedrich; Motz, Mario; Hammerschmidt, Dirk; Gastinger, Ferdinand; Schaffer, Bernhard; Granig, Wolfgang, Sensor self-diagnostics using multiple signal paths.
  22. Nauleau,Jean Luc; Erdelyi,Janos; McCalpin,William H., Systems and apparatus for digital control of bias for transistors.
  23. Irisawa, Tatsuya, Trimming circuit, power supply including trimming circuit, and trimming method.
  24. Lalithambika, Vinod A.; Garner, David M.; Coulson, David Robert; Ansari, Zahid, Trimming circuits and methods.
  25. John,Soji K.; Nguyen,Baoson; Mayhugh,Terry L., Trimming for accurate reference voltage.
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