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Method of forming a double gate transistor having an epitaxial silicon/germanium channel region 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
출원번호 US-0793055 (2001-02-26)
발명자 / 주소
  • Bin Yu
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Foley & Lardner
인용정보 피인용 횟수 : 363  인용 특허 : 18

초록

A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobi

대표청구항

1. A method of manufacturing an integrated circuit on a substrate, the method comprising:providing a fin area in the substrate; narrowing a width of the fin area by growing a sacrificial material on first sidewalls of the fin area and subsequently removing the sacrificial material to form second sid

이 특허에 인용된 특허 (18)

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  7. Masuoka Sadaaki,JPX, Method of fabricating CMOS semiconductor device.
  8. Yeh Wen-Kuan,TWX ; Lin Tony,TWX, Method of fabricating a metal-oxide-semiconductor transistor.
  9. Shimizu Kousaku,JPX, Method of fabricating polycrystalline silicon-germanium thin film transistor.
  10. Anjum Mohammed (Austin TX) Koop Klaus H. (Elgin TX) Kyaw Maung H. (Austin TX), Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold curr.
  11. Sameshima Toshiyuki (Kanagawa JPX) Hara Masaki (Kanagawa JPX) Sano Naoki (Kanagawa JPX) Gosain Dharam Pal (Kanagawa JPX) Usui Setsuo (Kanagawa JPX), Method of manufacturing Si-Ge thin film transistor.
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  14. Hamada Hiroki,JPX, Semiconductor device with high electric field effect mobility.
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  18. Sameshima Toshiyuki,JPX ; Hara Masaki,JPX ; Sano Naoki,JPX ; Gosain Dharam Pal,JPX ; Usui Setsuo,JPX, Thin film transistor and manufacturing method of the thin film transistor.

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