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Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • G03C-005/00
출원번호 US-0204166 (1998-12-03)
발명자 / 주소
  • Uzodinma Okoroanyanwu
  • Ramkumar Subramanian
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 29  인용 특허 : 12

초록

A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is an alicyclic polymer into which silicon is incorporated by liquid silylation, for example. The silicon-rich regions are con

대표청구항

1. A method of forming a damascene structure in a semiconductor device, comprising the steps of:forming a first low k dielectric layer; depositing an imageable layer comprising an alicyclic polymer on the first low k dielectric layer; patterning the first imageable layer to create a first patterned

이 특허에 인용된 특허 (12)

  1. Jung Jae Chang,KRX ; Bok Cheol Kyu,KRX ; Baik Ki Ho,KRX, ArF photoresist copolymers.
  2. Jung Jae Chang,KRX, Copolymer resin of maleimide and alicyclic olefin-based monomers, photoresist containing the copolymer resin and the preparation thereof.
  3. Dai Chang-Ming,TWX ; Huang Jammy Chin-Ming,TWX, Dual damascene process using single photoresist process.
  4. Jung Jae Chang,KRX ; Roh Chi Hyeong,KRX ; Park Joo On,KRX, Method and device using ArF photoresist.
  5. Hattori Takashi,JPX ; Tsuchiya Yuko,JPX ; Shiraishi Hiroshi,JPX, Method for pattern formation and process for preparing semiconductor device.
  6. Liao Kuan-Yang,TWX, Method of fabricating an opening with deep ultra-violet photoresist.
  7. Chow Ming-Fea (Poughquagh NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY), Method of forming fine conductive lines, patterns and connectors.
  8. Willson C. Grant ; Okoroanyanwu Uzodinma ; Medieros David, Photoresist compositions comprising norbornene derivative polymers with acid labile groups.
  9. Cote William J., Process of forming a dual damascene structure in a single photoresist film.
  10. Leveriza Carina T. (Milpitas CA) Morgan Russell A. (Eindhoven NLX), Silicon containing resists.
  11. Hutton Richard S. (Summit NJ) Taylor Gary N. (Bridgewater NJ) Wheeler David R. (Albuquerque NM), Surface-imaging technique for lithographic processes for device fabrication.
  12. Holmes Steven J. (Burlington VT), Vapor phase photoresist silylation process.

이 특허를 인용한 특허 (29)

  1. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  2. McAndrew, James J. F.; Anderson, Curtis; Dussarrat, Christian, Cyclic amino compounds for low-k silylation.
  3. Konishi, Nobuo; Iwashita, Mitsuaki, Film forming method and film forming apparatus.
  4. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  5. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  6. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  7. Lee,Sung Kwon; Moon,Seung Chan; Kim,Won Kyu, Method for fabricating fine pattern in semiconductor device.
  8. Nakagawa, Hideo; Tamaoka, Eiji, Method for fabricating semiconductor device.
  9. Lee,Date Gun, Method for forming metal pattern to reduce contact resistivity with interconnection contact.
  10. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  11. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  12. Ryu, Choon Kun, Method of forming a copper wiring in a semiconductor device.
  13. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  14. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  15. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  16. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  19. Russell, Noel M.; Newton, Kenneth Joseph; Jin, Changming, Methods for forming multiple damascene layers.
  20. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  21. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  22. Lu,Zhijian, Producing low k inter-layer dielectric films using Si-containing resists.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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