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[미국특허] Probe card for probing wafers with raised contact elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/26
출원번호 US-0204740 (1998-12-02)
발명자 / 주소
  • Benjamin N. Eldridge
  • Gary W. Grube
  • Gaetan L. Mathieu
출원인 / 주소
  • Formfactor, Inc.
인용정보 피인용 횟수 : 72  인용 특허 : 41

초록

A probe card is provided for contacting an electric componet with raised contact elements. In particular, the present invention is useful for contacting a semiconductor wafer with resilient contact elements, such as springs. A probe card is designed to have terminals to mate with the contact element

대표청구항

1. A probe card assembly for contacting a semiconductor device, the probe card assembly comprising:a probe card having interposer-contacting terminals disposed on a surface thereof; an interposer with opposing surfaces, having opposing pairs of contact structures extending from the opposing surfaces

이 특허에 인용된 특허 (41) 인용/피인용 타임라인 분석

  1. Small Gary L. (Los Gatos CA), Adaptable wafer probe assembly for testing ICs with different power/ground bond pad configurations.
  2. Driller Hubert (Schmitten DEX) Mang Paul (Schmitten DEX), Adapter arrangement for electrically connecting flat wire carriers.
  3. Ott Albert,DEX ; Tamm Wilhelm,DEX ; Laur Steffen,DEX ; Harr Volker,DEX, Adapter arrangement for electrically testing printed circuit boards.
  4. Ott Rainer,DEX, Adapter system for component assembly circuit boards, for use in a test device.
  5. Pivnichny John R. ; Underwood Joseph H., Apparatus and method for testing integrated circuit components of a multi-component card.
  6. Malladi Deviprasad (Campbell CA) Hanson Lee Frederick (Cupertino CA) Kahahane Jean (Redwood City CA), Apparatus for testing flip chip or wire bond integrated circuits.
  7. Buol Douglas A. (Dallas TX) Mize Dean N. (Garland TX) Pattschull John W. (Garland TX) Wallace Robert M. (Dallas TX), Apparatus for testing integrated circuits.
  8. Pasiecznik ; Jr. John (Malibu CA), Apparatus for testing integrated circuits.
  9. Yojima Masayuki,JPX ; Tsujide Tohru,JPX ; Nakaizumi Kazuo,JPX, Apparatus for testing semiconductor wafer.
  10. Takahashi Tadashi,JPX, Circuit board inspection apparatus and method.
  11. Kwon Oh-Kyong (Richardson TX) Malhi Satwinder (Garland TX) Hashimoto Masahi (Garland TX), Compliant contact pad.
  12. Khandros Igor Y. ; Mathieu Gaetan L., Composite interconnection element for microelectronic components, and method of making same.
  13. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L. ; Dozier Thomas H. ; Smith William D., Contact carriers (tiles) for populating larger substrates with spring contacts.
  14. Pih David, High density test connector for disk drives in a high volume manufacturing environment.
  15. Martel Anthony Paul ; McQuade Francis T., Impedance-matched interconnection device for connecting a vertical-pin integrated circuit probing device to integrated circuit test equipment.
  16. Khandros Igor Y. ; Pedersen David V. ; Eldridge Benjamin N. ; Roy Richard S. ; Mathieu Gaetan, Interconnect assemblies and methods including ancillary electronic component connected in immediate proximity of semiconductor device.
  17. Kasukabe Susumu (Yokohama JPX) Takagi Ryuichi (Tokyo JPX), Manufacturing method of a probe head for semiconductor LSI inspection apparatus.
  18. O'Connell Richard W., Method and apparatus for testing a semiconductor wafer.
  19. Hogl Erik ; Fiedler Ulrich, Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator.
  20. Palagonia Anthony Michael, Method for forming an interposer for making temporary contact with pads of a semiconductor chip.
  21. Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu, Method of fabricating an interconnection element.
  22. Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Method of making microelectronic spring contact elements.
  23. Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.
  24. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
  25. Akram Salman ; Farnworth Warren M. ; Wood Alan G. ; Hembree David R., Method, apparatus and system for testing bumped semiconductor components.
  26. Maddix John Thomas ; Palagonia Anthony Michael ; Pikna Paul Joseph ; Vallett David Paul, Micro probe ring assembly and method of fabrication.
  27. Sugihara Osamu (Nagasaka JPX), Microprobe provided circuit substrate and method for producing the same.
  28. Carney Eric Lane, Planarity verification system for integrated circuit test probes.
  29. Higgins H. Dan ; Pandey Rajiv ; Armendariz Norman J. ; Bates R. Dennis, Probe card assembly for high density integrated circuits.
  30. Trenary Dale T. (San Jose CA), Probe card for integrated circuit chip.
  31. Liu Jui-Hsiang (Chandler AZ) Olsen Dennis R. (Scottsdale AZ), Probe card for testing unencapsulated semiconductor devices.
  32. Mizuta Masaharu,JPX, Probe card with vertical needle for enabling improved wafer testing and method of manufacturing the same.
  33. Nakano Shoukichi (Kawasaki JPX), Prober for semiconductor integrated circuit element wafer.
  34. Hembree David R. ; Akram Salman, Semiconductor probe card having resistance measuring circuitry and method fabrication.
  35. Schmid Rainer,DEX ; Giringer Klaus,DEX ; Gauss Ulrich,DEX ; Deusch Heinz,DEX, Test head for microstructures with interface.
  36. Barrett Keith E., Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods.
  37. Beaman Brian Samuel ; Fogel Keith Edward ; Lauro Paul Alfred ; Norcott Maurice Heathcote ; Shih Da-Yuan ; Walker George Frederick, Test probe for high density integrated circuits, methods of fabrication thereof and methods of use thereof.
  38. Barabi Nasser, Test socket for an IC device.
  39. Nishikawa Hideo,JPX ; Miki Takashi,JPX, Universal printed circuit board inspection apparatus, and method of using same.
  40. Mizuta Masaharu,JPX, Vertical needle type probe card, method of manufacturing thereof, method of replacing defective probe needle and test method of wafer using the probe card.
  41. Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.

이 특허를 인용한 특허 (72) 인용/피인용 타임라인 분석

  1. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Cantilever microprobes for contacting electronic components and methods for making such probes.
  2. Chen, Richard T.; Kruglick, Ezekiel J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Cantilever microprobes for contacting electronic components and methods for making such probes.
  3. Chen,Richard T.; Kruglick,Ezekiel J. J.; Bang,Christopher A.; Smalley,Dennis R.; Lembrikov,Pavel B., Cantilever microprobes for contacting electronic components and methods for making such probes.
  4. Karavakis,Konstantine N.; Nguyen,Tom T., Connecting a probe card and an interposer using a compliant connector.
  5. Mok, Sammy; Chong, Fu Chiung; Swiatowiec, Frank John; Lahiri, Syamal Kumar; Haemer, Joseph Michael, Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs.
  6. Eldridge, Benjamin N., Electrical contactor, especially wafer level contactor, using fluid pressure.
  7. Eldridge, Benjamin N., Electrical contactor, especially wafer level contactor, using fluid pressure.
  8. Eldridge,Benjamin N., Electrical contactor, especially wafer level contactor, using fluid pressure.
  9. Eldridge,Benjamin N., Electrical contactor, especially wafer level contactor, using fluid pressure.
  10. Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Electrochemical fabrication process for forming multilayer multimaterial microprobe structures.
  11. Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Electrochemical fabrication process for forming multilayer multimaterial microprobe structures.
  12. Arat,Vacit; Cohen,Adam L.; Smalley,Dennis R.; Kruglick,Ezekiel J. J.; Chen,Richard T.; Kim,Kieun, Electrochemically fabricated microprobes.
  13. Haemer,Joseph Michael; Chong,Fu Chiung; Modlin,Douglas N., Enhanced compliant probe card systems having improved planarity.
  14. Cohen, Adam L.; Arat, Vacit; Lockard, Michael S.; Bang, Christopher A.; Lembrikov, Pavel B., Fabrication process for co-fabricating multilayer probe array and a space transformer.
  15. Bottoms, Wilmer R.; Chong, Fu Chiung; Mok, Sammy; Modlin, Douglas, High density interconnect system for IC packages and interconnect assemblies.
  16. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  17. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  18. Chong,Fu Chiung; Kao,Andrew; McKay,Douglas; Litza,Anna; Modlin,Douglas; Mok,Sammy; Parekh,Nitin; Swiatowiec,Frank John; Shan,Zhaohui, High density interconnect system having rapid fabrication cycle.
  19. Lee, Sang-hoon; Ko, Chang-woo; An, Young-soo; Oh, Se-jang, Interface structure of wafer test equipment.
  20. Kister, January, Layered probes with core.
  21. Kister, January, Low profile probe having improved mechanical scrub and reduced contact inductance.
  22. Chong, Fu Chiung; Mok, Sammy, Massively parallel interface for electronic circuit.
  23. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
  24. Di Stefano, Thomas H.; Di Stefano, Peter T., Method and apparatus for aligning and/or leveling a test head.
  25. Di Stefano, Thomas H.; Di Stefano, Peter T., Method and apparatus for aligning and/or leveling a test head.
  26. Eldridge, Benjamin N., Method of designing a probe card apparatus with desired compliance characteristics.
  27. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S., Method of making a contact.
  28. Tunaboylu,Bahadir; Hicklin,Jeff; Pipps,Ivan; Dang,Son; Back,Gerry, Method of probe tip shaping and cleaning.
  29. Derderian, James M., Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween.
  30. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  31. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  32. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  33. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S., Microprobe tips and methods for making.
  34. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S.; Bang,Christopher A., Microprobe tips and methods for making.
  35. Wu, Ming Ting; Larsen, III, Rulon Joseph; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material fabrication methods for producing micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  36. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  37. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  38. Kister, January, Multiple contact probes.
  39. Kister, January, Multiple contact probes.
  40. Kister, January; Beatson, David; Laurent, Edward, Prefabricated and attached interconnect structure.
  41. Kister,January; Beatson,David; Laurent,Edward, Prefabricated and attached interconnect structure.
  42. Kister, January, Probe bonding method having improved control of bonding material.
  43. Deguchi, Yoshinori, Probe card.
  44. Lee, Chung-Tse; Wu, Chien-Chou; Chen, Tsung-Yi; Chen, Ming-Chi, Probe card and manufacturing method thereof.
  45. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  46. Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W., Probe card assembly having an actuator for bending the probe substrate.
  47. Shinde, Makarand S.; Larder, Richard A.; Cooper, Timothy E.; Shenoy, Ravindra V.; Eldridge, Benjamin N., Probe card configuration for low mechanical flexural strength electrical routing substrates.
  48. Shinde,Makarand S.; Larder,Richard A.; Cooper,Timothy E.; Shenoy,Ravindra V.; Eldridge,Benjamin N., Probe card configuration for low mechanical flexural strength electrical routing substrates.
  49. Satou,Katsuhiko; Mori,Chikaomi; Nakashima,Masanari, Probe card for examining semiconductor devices on semiconductor wafers.
  50. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Probe devices formed from multiple planar layers of structural material with tip regions formed from one or more intermediate planar layers.
  51. Salmon, Jay; Swart, Roy E.; Liew, Brandon, Probe head assemblies and probe systems for testing integrated circuit devices.
  52. Kister, January; Shtarker, Alex, Probe retention arrangement.
  53. Kister, January; Shtarker, Alex, Probe retention arrangement.
  54. Kister, January, Probe skates for electrical testing of convex pad topologies.
  55. Karavakis, Konstantine N.; Nguyen, Tom T., Probe structures using clamped substrates with compliant interconnectors.
  56. Kister, January, Probes with high current carrying capability and laser machining methods.
  57. Kister, January, Probes with offset arm and suspension structure.
  58. Kister, January, Space transformers employing wire bonds for interconnections with fine pitch contacts.
  59. Karavakis, Konstantine N.; Nguyen, Tom T., Structures for testing circuits and methods for fabricating the structures.
  60. Karavakis,Konstantine N.; Nguyen,Tom T., Structures for testing circuits and methods for fabricating the structures.
  61. Mok, Sammy; Chong, Fu Chiung; Milter, Roman, Systems for testing and packaging integrated circuits.
  62. Bohm,Gunther, Test device for electrical testing of a unit under test.
  63. Bucksch,Thorsten, Test device for wafer testing digital semiconductor circuits.
  64. Miller, Charles A.; Cooper, Timothy E.; Hatsukano, Yoshikazu, Test method for yielding a known good die.
  65. Chen, Richard T.; Arat, Vacit; Folk, Chris; Cohen, Adam L., Two-part microprobes for contacting electronic components and methods for making such probes.
  66. Kister, January, Vertical guided layered probe.
  67. Kister, January, Vertical probe array arranged to provide space transformation.
  68. Kister, January, Vertical probe array arranged to provide space transformation.
  69. Eldridge, Benjamin N.; Reynolds, Carl V., Wafer level interposer.
  70. Eldridge,Benjamin N.; Reynolds,Carl V., Wafer level interposer.
  71. Johnson, Morgan T., Wafer prober integrated with full-wafer contacter.
  72. Johnson, Morgan T., Wafer prober integrated with full-wafer contactor.

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