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Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0927164 (2001-08-10)
우선권정보 JP-0270006 (1997-10-02)
발명자 / 주소
  • Koichi Hirano JP
  • Seiichi Nakatani JP
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd. JP
대리인 / 주소
    Merchant & Gould PC
인용정보 피인용 횟수 : 25  인용 특허 : 21

초록

A thermal conductive sheet including at least 70-95 weight parts of inorganic filler and 5-30 weight parts of thermosetting resin composition and having flexibility in an uncured state is prepared. Through-holes are formed in the thermal conductive sheet and a conductive resin composition is filled

대표청구항

1. A method for manufacturing a semiconductor package comprising:overlapping a semiconductor chip, comprising an electrode surface with at least one electrode disposed thereon and edge surfaces that adjoin the electrode surface, in a face down orientation on a thermal conductive sheet comprising at

이 특허에 인용된 특허 (21)

  1. Itagaki Minehiro (Moriguchi JPX) Okano Kazuyuki (Ikoma JPX) Kimura Suzushi (Toyonaka JPX) Nakatani Seiichi (Hirakata JPX) Bessho Yoshihiro (Higashiosaka JPX) Yuhaku Satoru (Osaka JPX) Hakotani Yasuhi, Assembly formed from conductive paste and insulating paste.
  2. Kawakita Kouji (Joyo JPX) Nakatani Seiichi (Hirakata JPX) Ogawa Tatsuo (Amagasaki JPX) Suehiro Masatoshi (Kyoto JPX) Iwaisako Kouichi (Uji JPX) Akiyama Hideo (Kyoto JPX), Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste.
  3. Kawakita Kouji,JPX ; Nakatani Seiichi,JPX ; Ogawa Tatsuo,JPX ; Suehiro Masatoshi,JPX ; Iwaisako Kouichi,JPX ; Akiyama Hideo,JPX, Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of ma.
  4. Kawakita Kouji,JPX ; Nakatani Seiichi,JPX ; Ogawa Tatsuo,JPX ; Suehiro Masatoshi,JPX ; Iwaisako Kouichi,JPX ; Akiyama Hideo,JPX, Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of ma.
  5. Kawakita Kouji,JPX ; Nakatani Seiichi,JPX ; Ogawa Tatsuo,JPX ; Suehiro Masatoshi,JPX ; Iwaisako Kouichi,JPX ; Akiyama Hideo,JPX, Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of ma.
  6. Booth Richard B. (Williamson County TX) Gaynes Michael A. (Broome County NY) Murco Robert M. (Broome County NY) Puligandla Viswanadham (Travis County TX) Roldan Judith M. (Westchester County NY) Sara, Direct chip attachment (DCA) with electrically conductive adhesives.
  7. Suzuki Masakazu (Kawasaki JPX), Electronic part unit or assembly having a plurality of electronic parts enclosed within a metal enclosure member mounted.
  8. Togawa Mitsuo,JPX ; Miyabayashi Kazuhiko,JPX ; Horie Takahiro,JPX ; Nara Naoki,JPX, Epoxy resin composition for semiconductor sealing and resin molded type semiconductor device sealed with the epoxy resin composition.
  9. Gilleo Kenneth Burton ; Blumel David, Flip chip with integrated mask and underfill.
  10. Tadauchi Masahiro,JPX ; Maezawa Yukishige,JPX ; Hayata Terunobu,JPX ; Shimada Hideki,JPX ; Ito Isao,JPX ; Suzuki Kazuo,JPX ; Tezuka Fuminobu,JPX ; Kano Jiro,JPX ; Gotanda Takeshi,JPX ; Koyama Masao,J, Method and apparatus for pyrolytically decomposing waste plastic.
  11. Petefish William George ; Piper Boydd, Method for aligning and laminating substrates to stiffeners in electrical circuits.
  12. Kuboki Kenichi,JPX ; Kajiwara Yoshitaka,JPX ; Shimamura Yoshio,JPX ; Akatsuka Yasumasa,JPX, Modified epoxy resin, epoxy resin composition and cured product thereof.
  13. Sawai Akiyoshi (Hyogo JPX) Shimamoto Haruo (Hyogo JPX) Tachikawa Toru (Hyogo JPX) Shibata Jun (Hyogo JPX), Plastic molded semiconductor package.
  14. Sawai Akiyoshi,JPX ; Shimamoto Haruo,JPX ; Tachikawa Toru,JPX ; Shibata Jun,JPX, Plastic molded semiconductor package and method of manufacturing the same.
  15. Sawai Akiyoshi,JPX ; Shimamoto Haruo,JPX ; Tachikawa Toru,JPX ; Shibata Jun,JPX, Plastic molded semiconductor package and method of manufacturing the same.
  16. Sawai Akiyoshi,JPX ; Shimamoto Haruo,JPX ; Tachikawa Toru,JPX ; Shibata Jun,JPX, Plastic molded semiconductor package and method of manufacturing the same.
  17. Ichiyama Hideyuki (Itami JPX), Resin-sealed semiconductor device.
  18. Murakami Gen (Machida JPX) Tsubosaki Kunihiro (Hino JPX) Ichitani Masahiro (Kodaira JPX) Nishi Kunihiko (Kokubunji JPX) Anjoh Ichiro (Koganei JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Shimoinay, Semiconductor device.
  19. Kunitomo Yoshinobu (Kyoto JPX) Nozu Makoto (Kyoto JPX) Sakashita Yasuyuki (Shiga JPX) Tsukamoto Masahide (Nara JPX) Nakatani Seiichi (Osaka JPX) Saeki Keiji (Hyogo JPX) Kitayama Yoshifumi (Osaka JPX), Semiconductor device and method of manufacturing the same.
  20. Kunitomo Yoshinobu (Kyoto JPX) Nozu Makoto (Kyoto JPX) Sakashita Yasuyuki (Shiga JPX) Tsukamoto Masahide (Nara JPX) Nakatani Seiichi (Osaka JPX) Saeki Keiji (Hyogo JPX) Kitayama Yoshifumi (Osaka JPX), Semiconductor device and method of manufacturing the same.
  21. Nakatani Seiichi,JPX ; Handa Hiroyuki,JPX, Sheet for a thermal conductive substrate, a method for manufacturing the same, a thermal conductive substrate using the sheet and a method for manufacturing the same.

이 특허를 인용한 특허 (25)

  1. Weng, Chaofu; Wu, Yi Ting, Chip package structure and manufacturing methods thereof.
  2. Lee, Chang-Chi; Chen, Shih-Kuang; Chang, Yuan-Ting, Chip package structure and method of manufacturing the same.
  3. Kohara, Yasuhiro; Usui, Ryosuke; Mizuhara, Hideki; Inoue, Yasunori, Circuit device with circuit board and semiconductor chip mounted thereon.
  4. Lee, Chun-Che; Su, Yuan-Chang; Lee, Ming Chiang; Huang, Shih-Fu, Embedded component device and manufacturing methods thereof.
  5. Su, Yuan-Chang; Huang, Shih-Fu; Lee, Ming-Chiang; Wang, Chien-Hao, Embedded component substrate and manufacturing methods thereof.
  6. Sakurai,Daisuke; Tsukahara,Norihito, Manufacturing method for electronic component-mounted component, manufacturing method for electronic component-mounted completed product with the electronic component-mounted component, and electroni.
  7. Maeng,Duck Young; Sun,Byung Kook; Kim,Tae Hoon; Mok,Jee Soo; Bae,Jong Suk; Oh,Yoong; Song,Chang Kyu; Cho,Suk Hyeon, Method of manufacturing package substrate with fine circuit pattern using anodic oxidation.
  8. Lucas,Kevin D.; Cobb,Jonathan L.; Wilkinson,William L., Non-resolving mask tiling method for flare reduction.
  9. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng, Package carrier, semiconductor package, and process for fabricating same.
  10. Muta, Tadayoshi, Semiconductor apparatus manufacturing method and semiconductor apparatus.
  11. Saigoh, Kaoru; Nagai, Kouichi, Semiconductor device having a ferroelectric capacitator.
  12. Hsieh, Chuehan; Yang, Hung-Jen; Huang, Min-Lung, Semiconductor device package with an alignment mark.
  13. Ding, Yi-Chuan; Chen, Chia-Ching, Semiconductor device packages including connecting elements.
  14. Ding, Yi-Chuan; Chen, Chia-Ching, Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof.
  15. Yang, Hung-Jen; Hsieh, Chuehan; Huang, Min-Lung, Semiconductor device packages, redistribution structures, and manufacturing methods thereof.
  16. Haji, Hiroshi; Sakemi, Shoji, Semiconductor device with reinforcing resin layer.
  17. Chen, Chia-Ching; Ding, Yi-Chuan, Semiconductor package including a stacking element.
  18. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
  19. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
  20. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
  21. Chen, Chia-Ching; Ding, Yi-Chuan, Stackable semiconductor package and manufacturing method thereof.
  22. Hunt, John Richard, Wafer level semiconductor package and manufacturing methods thereof.
  23. Hunt, John Richard, Wafer level semiconductor package and manufacturing methods thereof.
  24. Chiu, Chi-Tsung; Liao, Kuo-Hsien; Yih, Wei-Chi; Chen, Yu-Chi; Fan, Chen-Chuan, Wafer-level semiconductor device packages with electromagnetic interference shielding.
  25. Lee, Ming-Chiang; Wang, Chien-Hao, Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof.
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