초록 ▼

An architecture, system and method are provided for efficiently transferring data across multiple processor buses. Cache coherency is maintained among cache storage locations within one or more of those processors, even in instances where a hit-to-modified condition occurs to those cache storage loc

An architecture, system and method are provided for efficiently transferring data across multiple processor buses. Cache coherency is maintained among cache storage locations within one or more of those processors, even in instances where a hit-to-modified condition occurs to those cache storage locations. A guaranteed access is maintained to bus agents operating on a first processor bus so that out-of-order or split transactions are prevented on that bus even under conditions of a hit-to-modified condition. One or more of the other processor buses undergo a defer transaction, yielding an out-of-order condition which is resolved after the initial transaction and a snoop request cycle has been placed upon the first processor bus. The present architecture, system and method thereby prevents live-lock conditions, and does so without automatically deferring each transaction yielding a hit-to-modified signal. Moreover, snoop stall operations can also be minimized or avoided on processor buses by not having to employ tag filters and local memory if the costs and latency involved with using such filters is not desired.

대표청구항 ▼

1. A bus interface unit coupled between a first bus and a second bus, said bus interface unit comprising an arbiter coupled to allow completion of a first transaction within the first bus and initiation of a snoop request cycle to a modified cache line within a first bus agent coupled to the first b

1. A bus interface unit coupled between a first bus and a second bus, said bus interface unit comprising an arbiter coupled to allow completion of a first transaction within the first bus and initiation of a snoop request cycle to a modified cache line within a first bus agent coupled to the first bus before granting mastership to the second bus.