$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Non-metallic barrier formations for copper damascene type interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0925821 (2001-08-10)
발명자 / 주소
  • Simon Chooi SG
  • Subhash Gupta SG
  • Mei-Sheng Zhou SG
  • Sangki Hong SG
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd. SG
대리인 / 주소
    George O. Saile
인용정보 피인용 횟수 : 21  인용 특허 : 7

초록

A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in mic

대표청구항

1. A method for forming a dual-damascene type conducting interconnect within a microelectronics fabrication, comprising:providing a layered structure such as is used in a microelectronics fabrication, said structure comprising a conducting layer, on which has been formed a passivating layer, on whic

이 특허에 인용된 특허 (7)

  1. Harper James M. E. ; Geffken Robert M., Copper stud structure with refractory metal liner.
  2. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  3. Stolmeijer Andre, Interconnect scheme for integrated circuits.
  4. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  5. Iguchi Katsuji,JPX ; Doi Tsukasa,JPX ; Murakami Masanori,JPX ; Oku Takeo,JPX, Method for fabricating a semiconductor device having copper layer.
  6. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  7. Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.

이 특허를 인용한 특허 (21)

  1. Brennan, Kenneth D., Aluminum hardmask for dielectric etch.
  2. Cheung, David; Yau, Wai-Fan; Mandal, Robert R., Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds.
  3. Woo, Christy Mei-Chu; Ngo, Minh Van; Sanchez, Jr., John E.; Avanzino, Steven C., Conformal barrier liner in an integrated circuit interconnect.
  4. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
  5. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
  6. Bedinger, John M.; Moore, Michael A., Environmental protection coating system and method.
  7. Cooney, III, Edward C; Fitzsimmons, John A; Gambino, Jeffrey P; Luce, Stephen E; McDevitt, Thomas L; Nicholson, Lee M; Stamper, Anthony K, Exposed pore sealing post patterning.
  8. Cooney, III,Edward C.; Fitzsimmons,John A.; Gambino,Jeffrey P.; Luce,Stephen E.; McDevitt,Thomas L.; Nicholson,Lee M.; Stamper,Anthony K., Exposed pore sealing post patterning.
  9. King,Sean W.; Ott,Andrew W., Integrated low-k hard mask.
  10. Yau, Wai-Fan; Cheung, David; Jeng, Shin-Puu; Liu, Kuowei; Yu, Yung-Cheng, Method of depositing a low K dielectric with organo silane.
  11. Yau, Wai-Fan; Cheung, David; Jeng, Shin-Puu; Liu, Kuowei; Yu, Yung-Cheng, Method of depositing a low dielectric with organo silane.
  12. Huang, Tzu-Fang; Lu, Yung-Cheng; Xia, Li-Qun; Yieh, Ellie; Yau, Wai-Fan; Cheung, David W.; Willecke, Ralf B.; Liu, Kuowei; Lee, Ju-Hyung; Moghadam, Farhad K.; Ma, Yeming Jim, Method of depositing low K films.
  13. Bedinger, John M.; Moore, Michael A., Methods of making an environment protection coating system.
  14. Kim, Bok Hoen; Rathi, Sudha; Ahn, Sang H.; Bencher, Christopher D.; Wang, Yuxiang May; M'Saad, Hichem; Silvetti, Mario D.; Fung, Miguel; Jung, Keebum; Zhu, Lei, Nitrogen-free dielectric anti-reflective coating and hardmask.
  15. Kim,Bok Hoen; Rathi,Sudha; Ahn,Sang H.; Bencher,Christopher D.; Wang,Yuxiang May; M'Saad,Hichem; Silvetti,Mario D., Nitrogen-free dielectric anti-reflective coating and hardmask.
  16. Bedinger, John M.; Moore, Michael A.; Hallock, Robert B.; Alavi, Kamal Tabatabaie; Kazior, Thomas E., Passivation layer for a circuit device and method of manufacture.
  17. Bedinger, John; Moore, Michael A.; Hallock, Robert B; Tabatabaie, Kamal; Kazior, Thomas E., Passivation layer for a circuit device and method of manufacture.
  18. Cheung, David; Yau, Wai-Fan; Mandal, Robert P.; Jeng, Shin-Puu; Liu, Kuo-Wei; Lu, Yung-Cheng; Barnes, Michael; Willecke, Ralf B.; Moghadam, Farhad; Ishikawa, Tetsuya; Poon, Tze Wing, Plasma processes for depositing low dielectric constant films.
  19. Cheung, David; Yau, Wai-Fan; Mandal, Robert P.; Jeng, Shin-Puu; Liu, Kuo-Wei; Lu, Yung-Cheng; Barnes, Michael; Willecke, Ralf B.; Moghadam, Farhad; Ishikawa, Tetsuya; Poon, Tze Wing, Plasma processes for depositing low dielectric constant films.
  20. Hamada, Masakazu; Maekawa, Kazuyoshi; Mori, Kenichi, Semiconductor device and method for fabricating the same.
  21. Bae, Se Yeul, Semiconductor device with a metal line and method of forming the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로