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Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0667837 (2000-09-22)
발명자 / 주소
  • Shyue Fong Quek MY
  • Ying Keung Leung SG
  • Sang Yee Loong SG
  • Ting Cheong Ang SG
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd. SG
대리인 / 주소
    George O. Saile
인용정보 피인용 횟수 : 170  인용 특허 : 8

초록

In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package a

대표청구항

or more semiconductor supporting units that provide mechanical support for mounting said one or more semiconductor devices and that further function as electrical insulators and heat conductor units between said one or more semiconductor devices, said one or more semiconductor supporting units havin

이 특허에 인용된 특허 (8)

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  8. Jeong Do Soo,KRX ; An Min Cheol,KRX ; Ahn Seung Ho,KRX ; Jeong Hyeon Jo,KRX ; Choi Ki Won,KRX, Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements.

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