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Semi-sacrificial diamond for air dielectric formation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
  • H01L-029/80
  • H01L-031/112
  • H01L-029/00
출원번호 US-0825653 (2001-04-04)
발명자 / 주소
  • Lawrence A. Clevenger
  • Louis Lu-Chen Hsu
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Judith D. Olsen
인용정보 피인용 횟수 : 28  인용 특허 : 4

초록

Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an

대표청구항

1. A process for providing a gaseous dielectric medium within a multilevel interconnect integrated circuit chip, comprising the steps of:a. providing a multilevel interconnect integrated circuit chip structure which includes a CVD diamond semi-sacrificial dielectric medium; b. providing a hard mask

이 특허에 인용된 특허 (4)

  1. Reyes Gregory R. ; Yarbough Patrice O. ; Bradley Daniel W. ; Krawczynski Krzysztof Z. ; Tam Albert ; Fry Kirk E., DNA sequences of enterically transmitted non-A/non-B hepatitis viral agent.
  2. Aitken John M. (Mahopac NY) Beyer Klaus D. (Poughkeepsie NY) Crowder Billy L. (Putnam Valley NY) Greco Stephen E. (Lagrangeville NY), Larce scale IC personalization method employing air dielectric structure for extended conductors.
  3. Lur Water,TWX ; Wu Jiunn Yuan,TWX, Multi-level conduction structure for VLSI circuits.
  4. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (28)

  1. Chiu, Chia-Pin; Qian, Zhiguo; Manusharow, Mathew J., Bridge interconnect with air gap in package assembly.
  2. Chiu, Chia-Pin; Qian, Zhiguo; Manusharow, Mathew J., Bridge interconnect with air gap in package assembly.
  3. Chiu, Chia-Pin; Qian, Zhiguo; Manusharow, Mathew J., Bridge interconnect with air gap in package assembly.
  4. Downey,Stephen; Harris,Edward; Merchant,Sailesh, Capacitor for integration with copper damascene processes and a method of manufacture therefore.
  5. Bielefeld, Jeffery D.; Boyanov, Boyan, Dielectric spacers for metal interconnects and method to form the same.
  6. Hussein, Makarem A.; Boyanov, Boyan, Dielectric spacers for metal interconnects and method to form the same.
  7. Hussein, Makarem A.; Boyanov, Boyan, Dielectric spacers for metal interconnects and method to form the same.
  8. Natzle,Wesley C., Freestanding multiplayer IC wiring structure.
  9. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  10. Chinthakindi,Anil K.; Groves,Robert A.; Tretiakov,Youri V.; Vaed,Kunal; Volant,Richard P., Method of forming suspended transmission line structures in back end of line processing.
  11. Lin, Charles, Method of making an ultimate low dielectric device.
  12. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  13. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.
  14. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.
  15. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package with conductive elements and associated method of manufacture.
  16. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device with package with conductive elements and associated method of manufacture.
  17. Babich, Katherina E.; Carruthers, Roy Arthur; Dalton, Timothy Joseph; Grill, Alfred; Hedrick, Jeffrey Curtis; Jahnes, Christopher Vincent; Mays, Ebony Lynn; Perraud, Laurent; Purushothaman, Sampath; , Multilayer interconnect structure containing air gaps and method for making.
  18. Babich,Katherina E.; Carruthers,Roy Arthur; Dalton,Timothy Joseph; Grill,Alfred; Hedrick,Jeffrey Curtis; Jahnes,Christopher Vincent; Mays,Ebony Lynn; Perraud,Laurent; Purushothaman,Sampath; Saenger,K, Multilayer interconnect structure containing air gaps and method for making.
  19. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  20. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  21. Townsend, III, Paul H.; Foster, Kenneth L., Process for making air gap containing semiconducting devices and resulting semiconducting device.
  22. Boyanov, Boyan, Self-enclosed asymmetric interconnect structures.
  23. Boyanov, Boyan; Singh, Kanwal Jit; Clarke, James; Myers, Alan, Semiconductor interconnect structures.
  24. Boyanov, Boyan; Singh, Kanwal Jit; Clarke, James; Myers, Alan, Semiconductor interconnect structures.
  25. Boyanov, Boyan; Singh, Kanwal; Clarke, James; Myers, Alan, Semiconductor interconnect structures.
  26. Boyanov, Boyan; Singh, Kanwal; Clarke, James; Myers, Alan, Semiconductor interconnect structures.
  27. Farrar, Paul A., Structures and methods to enhance copper metallization.
  28. Chinthakindi, Anil K.; Groves, Robert A.; Tretiakov, Youri V.; Vaed, Kunal; Volant, Richard P., Suspended transmission line structures in back end of line processing.
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