초록 ▼

A method and apparatus is provided for determining the efficiency of an air preconditioning module having an energy transfer matrix disposed between a supply air flow to a building, and a return air flow from the building. In particular, a predetermined relationship is determined between pressure dr

A method and apparatus is provided for determining the efficiency of an air preconditioning module having an energy transfer matrix disposed between a supply air flow to a building, and a return air flow from the building. In particular, a predetermined relationship is determined between pressure drop across measured across the matrix and the efficiency of the matrix.

대표청구항 ▼

A method and apparatus is provided for determining the efficiency of an air preconditioning module having an energy transfer matrix disposed between a supply air flow to a building, and a return air flow from the building. In particular, a predetermined relationship is determined between pressure dr

A method and apparatus is provided for determining the efficiency of an air preconditioning module having an energy transfer matrix disposed between a supply air flow to a building, and a return air flow from the building. In particular, a predetermined relationship is determined between pressure drop across measured across the matrix and the efficiency of the matrix. identify faulty locations in said array, wherein said faults are identified by assertion of an error signal; and a BISR unit coupled to said memory array and configured to intercept addresses directed to said memory array, wherein during a training phase, the BISR unit is configured to store the intercepted addresses when the error signal is asserted, wherein during normal operation, the BISR unit is configured to compare all intercepted addresses to stored addresses to redirect a corresponding memory access if any intercepted address matches a stored address, and wherein during a verification phase, the BISR unit is configured to compare intercepted addresses designated by assertions of the error signal to addresses stored in the training phase; wherein the BISR unit comprises: a counter coupled to receive the error signal and configured to increment an error count only when the error signal is asserted; a decoder coupled to the counter to receive the error count, and configured to assert a decoder signal line that corresponds to the error count; one or more redundant location stages each coupled to receive the error signal and a corresponding decoder signal line; and a logic gate coupled to each of the stages and configured to assert a "new error" signal if none of said stages indicates a match between an intercepted address and a stored address during assertion of the error signal in the verification phase. 4. The memory device of claim 3, further comprising: a second logic gate coupled to each of the stages and configured to assert a "missed error" signal if at least one of said stages indicates a stored address failed to match at least one intercepted address designated by assertion of the error signal. 5. The memory device of claim 3, wherein each stage includes: a storage module configured to store the intercepted address during the training phase if the error signal and the corresponding decoder signal line are asserted; and a comparison module configured to receive the intercepted address and coupled to the storage module to receive the stored address, wherein the comparison module is configured to assert a match signal when the intercepted address matches the stored address, wherein said logic gate is configured to generate said new error signal responsive to the match signals from each stage, the error signal, and a mode signal. 6. The memory device of claim 5, wherein each stage further comprises: a tracking module configured to receive the match signal and configured to latch a "hit" signal if the match signal and the error signal are asserted during the verification phase. 7. The memory module of claim 6, wherein each stage further comprises: an address filter module configured to delay the intercepted address while the comparison module generates the match signal, and further configured to block the intercepted address signal if the comparison module asserts the match signal outside the verification phase. ISK STORAGE SYSTEM EMPLOYING ERROR DETECTION AND CORRECTION OF CHANNEL CODED DATA, INTERPOLATED TIMING RECOVERY, AND RETROACTIVE/SPLIT-SEGMENT SYMBOL SYNCHRONIZATION." The above-identified U.S. patent applications and U.S. patents are incorporated herein by reference.