초록 ▼

Methods and apparatus for controlling an automated material handling procedure. The method includes receiving a recipe file comprising component information and mapping information; interacting with a user to create a procedure for executing a set of material handling steps; and causing a automated

Methods and apparatus for controlling an automated material handling procedure. The method includes receiving a recipe file comprising component information and mapping information; interacting with a user to create a procedure for executing a set of material handling steps; and causing a automated material-handling apparatus to carry out the set of material-handling steps by executing the procedure. The mapping information relates a source component and a destination component. The mapping information defines one or more transfers of at least one source component material to at least one destination component location. The method includes providing to the user an assortment of pre-programmed code objects and receiving from the user a selection and arrangement of the pre-programmed code objects. The procedure is defined by the user's selection and arrangement. The procedure contains at least one first pre-programmed code object operable to read and interpret the recipe file and at least one second pre-programmed code object operable to interpret a mapping read from the recipe file.

대표청구항 ▼

Methods and apparatus for controlling an automated material handling procedure. The method includes receiving a recipe file comprising component information and mapping information; interacting with a user to create a procedure for executing a set of material handling steps; and causing a automated

Methods and apparatus for controlling an automated material handling procedure. The method includes receiving a recipe file comprising component information and mapping information; interacting with a user to create a procedure for executing a set of material handling steps; and causing a automated material-handling apparatus to carry out the set of material-handling steps by executing the procedure. The mapping information relates a source component and a destination component. The mapping information defines one or more transfers of at least one source component material to at least one destination component location. The method includes providing to the user an assortment of pre-programmed code objects and receiving from the user a selection and arrangement of the pre-programmed code objects. The procedure is defined by the user's selection and arrangement. The procedure contains at least one first pre-programmed code object operable to read and interpret the recipe file and at least one second pre-programmed code object operable to interpret a mapping read from the recipe file. el for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern. 4. A system for designing a semiconductor integrated circuit, comprising: means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern; means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern; means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern; means for deciding whether the evaluated value satisfies a predetermined condition; and means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition. 5. A system according to claim 4, wherein the pattern formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for lithography or data for electron beam lithography. 6. A system according to claim 4, wherein the pattern formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern. 7. A computer readable medium configured to store program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition. mber greater or equal to one. 7. The system of claim 1 wherein said complementary logic circuit is constructed utilizing silicon on insulator technology. 8. The system of claim 1 further comprising multiplexing means within said complement tree for selectively replacing said complement signal with said true signal within said complement tree, such that said true tree may be utilized to rectify a non-complementary logic condition at the output of said complementary logic circuit. 9. The system of claim 8 wherein said multiplexing means includes a true input select signal and a complement input select signal. 10. The system of claim 9 wherein said true input select signal is utilized for selectively replacing said true signal with said complement signal and said complement input select signal is utilized for selectively replacing said complement signal with said true signal. 11. The system of claim 10 wherein said multiplexing means is comprised of a first and a second tristate inverter, said first tristate inverter receiving at least one input control signal from said true input select signal, said second tristate inverter receiving at least one input control signal from said complement input select signal. 12. The system of claim 10 further comprising a test enable circuit for ensuring that said true input select signal and said complement input select signal are not simultaneously enabled. 13. A method for correcting a proscribed non-complementary output from a complementary logic circuit having a true tree and a complement tree, said method comprising the steps of: generating a true signal utilizing said true tree, said true signal utilized to produce a true output signal from said complementary logic circuit, and generating a complement signal utilizing said complement tree, said complement signal utilized to produce a complement output signal from said complementary logic circuit; and selectively replacing said true signal with said complement signal within said true tree, such that said complement tree may be utilized to rectify a non-complementary condition at the output of said complementary logic circuit. 14. The method of claim 13 wherein said step of selectively replacing said true signal with said complement signal comprises multiplexing said complement signal into said true tree. 15. The method of claim 13 further comprising the step of selectively replacing said complement signal with said true signal within said complement tree, such that said true tree may be utilized to rectify a non-complementary condition at the output of said complementary logic circuit. 16. The method of claim 15 wherein said step of selectively replacing said complement signal with said true signal comprises multiplexing said true signal into said complement tree. ding information of structures having outer boundary boxes completely or partially in a window, and generating information of the window view from the information thus included in the build file. In generating the build file, information of structures having outer boundary boxes completely outside the window are excluded from the build file. Also excluded is information of structures having areas less than a threshold value.