[특허]Reformed natural gas for powering an internal combustion engine

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특허 상세정보

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Reformed natural gas for powering an internal combustion engine

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	F02M-027/02
미국특허분류(USC)	123/003
출원번호	US-0541541 (2000-04-03)
발명자 / 주소	Collier, Jr., R. Kirk
대리인 / 주소	Christie, Parker & Hale, LLP
인용정보	피인용 횟수 : 155 인용 특허 : 46

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A method of operating an internal combustion engine comprising the steps of providing an internal combustion engine and a source of gaseous fuel such as natural gas or propane for powering the engine. Also, there is provided a reactor in fluid communication with said engine for reforming the gaseous fuel. The natural gas is added to the reactor for purposes of converting or reforming a portion of the natural gas to H2and CO to provide a gaseous mixture exiting the reactor comprised of methane, H2and CO. The gaseous mixture is mixed with air to provide a gaseous mixture and air combination. The gaseous mixture and air combination is introduced to the internal combustion engine and combusted to provide an exhaust gas. A portion of the exhaust gas is recycled and introduced to the reactor for purposes of reforming the gaseous fuel. on film in the gate electrode and said high concentration diffusion layer of said peripheral circuit-forming region; and (i) removing said metal layer remaining unreacted, and forming a second insulating film over the memory cell-forming region and the peripheral circuit-forming region. 3. The method for fabricating a semiconductor integrated circuit device according to claim 2, further comprising the steps of: (j) depositing a third insulating film on said second insulating film and removing the second insulating film and the third insulating film so as to form a contact hole over the silicide film formed over the polysilicon film of said peripheral circuit-forming region or over the high concentration diffusion layer; and (k) burying a conductive film in the contact hole. 4. The method for fabricating a semiconductor integrated circuit device according to claim 3, wherein said n channel-type MISFET or said p channel-type MISFET is formed in a region surrounded by an isolation region, and said contact hole extends over said isolation region. 5. A method for fabricating a semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and a SRAM memory cell having an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, the method comprising the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) successively forming a polysilicon film and a high melting metal film on the gate insulating film, followed by patterning in a desired form to form a gate electrode in a memory cell-forming region and in a peripheral circuit-forming region, respectively; (c) injecting an impurity at both sides of the gate electrode to form a low concentration diffusion layer; (d) depositing a first insulating film on the gate electrode; (e) anisotropically etching the first insulating film formed in the peripheral circuit-forming region to form a side wall film on side walls of the gate electrode formed in the peripheral circuit-forming region; (f) injecting an impurity into the peripheral circuit-forming region using the side wall film as a mask to form a high concentration diffusion layer; (g) removing the high melting metal film from the gate electrode of the peripheral circuit-forming region; (h) depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film in the gate electrode and also on the high concentration diffusion layer of the peripheral circuit-forming region; and (i) removing the metal layer remaining unreacted, and forming a second insulating film over the memory cell-forming region and the peripheral circuit-forming region. 6. The method for fabricating a semiconductor integrated circuit device according to claim 5, further comprising the steps of: (j) depositing a third insulating film on the second insulating film and removing the second insulating film and the third insulating film so as to form a contact hole extending from the polysilicon film in the gate electrode of the p channel-type MISFET to the silicide film over the high concentration diffusion layer of the n channel-type MISFET; and (k) burying a conductive film in the contact hole to form a wiring. 7. The method for fabricating a semiconductor integrated circuit device according to claim 5, further comprising the steps of: (j) depositing a third insulating film on the second insulating film and removing the second insulating film and the third insulating film so as to form a contact hole extending from the polysilicon film in the gate electrode of the n channel-type MISFET to the silicide film over the high concentration diffusion layer of the p channel-type MISFET; and (k) burying a conductive film in the contact hole to form a wiring. 8. A method for fabricating a semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, the method comprising the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) successively forming a polysilicon film, a high melting metal film and a silicon nitride film on said gate insulating film, followed by patterning in a desired form to form a gate electrode in the memory cell-forming region and in the peripheral circuit-forming region, respectively; (c) injecting an impurity at both sides of said gate electrode to form a low concentration diffusion layer; (d) depositing a first insulating film on said gate electrode; (e) anisotropically etching said first insulating film formed in the peripheral circuit-forming region to form a side wall film on side walls of the gate electrode formed in the peripheral circuit-forming region; (f) injecting an impurity into the peripheral circuit-forming region using the side wall film as a mask to form a high concentration diffusion layer; (g) removing the high melting metal film and the silicon nitride film from the gate electrode of said peripheral circuit-forming region; (h) depositing a metal layer over said peripheral circuit-forming region, followed by thermal treatment to form a silicide film on said polysilicon film in the gate electrode and also on said high concentration diffusion layer of said peripheral circuit-forming region; and (i) removing said metal layer remaining unreacted, and forming a second insulating film over the memory cell-forming region and the peripheral circuit-forming region. 9. A method for fabricating a semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, the method comprising the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) successively forming a polysilicon film and a high melting metal film on the gate insulating film; (c) subjecting the gate insulating film, the polysilicon film and the high melting metal film over the peripheral circuit-forming region to patterning thereby forming a gate electrode in the peripheral circuit-forming region; (d) injecting an impurity at both sides of the gate electrode of the peripheral circuit-forming region to form a low concentration diffusion layer; (e) depositing a first insulating film on the gate electrode of the peripheral circuit-forming region; (f) anisotropically etching the first insulating film to form a side wall film on side walls of the gate electrode of the peripheral circuit-forming region; (g) injecting an impurity into the peripheral circuit-forming region using the side wall film as a mask to form a high concentration diffusion layer; (h) removing the high melting metal film from the gate electrode of the peripheral circuit-forming region; (i) depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film of the gate electrode and the high concentration diffusion layer of the peripheral circuit-forming region; (j) removing the metal layer remaining unreacted; and (k) subjecting the gate insulating film, the polysilicon film, the high melting metal film and a second insulating film formed over the memory cell-forming region to patterning to form a gate electrode in the memory cell-forming region.

이 특허에 인용된 특허 (46)

이 특허를 인용한 특허 피인용횟수: 155

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Reformed natural gas for powering an internal combustion engine

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이 특허에 인용된 특허 (46)

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Reformed natural gas for powering an internal combustion engine

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이 특허에 인용된 특허 (46)

이 특허를 인용한 특허 피인용횟수: 155

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