[특허]Network switch with head of line input buffer queue clearing

Fairchild Semiconductor Corporation

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Network switch with head of line input buffer queue clearing

국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04L-012/56
미국특허분류(USC)	370/236; 370/415; 370/429
출원번호	US-0258181 (1999-02-25)
발명자 / 주소	Pannell, Donald Robert
출원인 / 주소	Fairchild Semiconductor Corporation
대리인 / 주소	Bedell, Daniel J.Smith-Hill and Bedell
인용정보	피인용 횟수 : 113 인용 특허 : 7

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An improvement is provided to a network switch of the type including a set of input and output ports for receiving and forwarding data transmissions from and to network stations and a crosspoint switch for selectively routing data transmissions between the input and output ports. Each input port stores successive incoming data transmissions in an input buffer queue. When a data transmission reaches the head of the queue, the input port requests a route through the crosspoint switch to an output port that is to forward the transmission to a network station. When the output port is ready to receive the transmission the crosspoint switch establishes the route and the input port forwards the data transmission from its buffer queue to the output port. In the improved network switch, the input port discards the data transmission at the head of the buffer queue without forwarding it to an output port when necessary to make room in the buffer for incoming transmissions. ion transmission system to operate as the standby system, and first and second delay circuits respectively corresponding to the first and second information transmission systems, the first delay circuit providing a time-delay to the switching request signal to be fed from the first external switching circuit to the second internal switching circuit and the second delay circuit providing a time-delay to the switching request signal to be fed from the second external switching circuit to the first internal switching circuit, in order to perform switching operations between the standby state and active state in the first and second information transmission systems during the same frame of pulses corresponding to the first and second information transmission systems. 2. The non-break change-over device defined in claim 1, wherein each timing pulse for each of the first and second information transmission systems is out of phase with the frame pulse by about half the period for each of the corresponding first and second information transmission systems. 3. The non-break change-over device defined in claim 1, wherein when the first information transmission system is functioning as the standby system, the first internal switching circuit receives the switching instruction signal from the monitoring section through the second external switching circuit, the first internal switching circuit outputs the internal switching signal during a first frame subsequent to a frame during which the second external switching circuit receives the switching instruction signal, and at a time of a head of a frame following the first frame, the first external switching circuit outputs the switching request signal toward the second internal switching circuit; and when the second information transmission system is functioning as the standby system, the second internal switching circuit receives the switching instruction signal from the monitoring section through the first external switching circuit, the second internal switching circuit outputs the internal switching signal during a second frame subsequent to a frame during which the first external switching circuit receives the switching instruction signal, and at a time of a head of a frame following the second frame, the second external switching circuit outputs the switching request signal toward the first internal switching circuit. 4. The non-break change-over device defined in claim 1, wherein the first and second delay circuits operate in synchronization with the frame pulse for the first and second information transmission systems, respectively, wherein the first delay circuit comprises one first holding circuit to hold the switching request signal to be sent to the second information transmission system when the frame pulse is received, the first internal switching circuit operating in synchronization with the timing pulse for the first information transmission system, and one second holding circuit to hold the switching request signal fed by the first holding circuit when the timing pulse is received; and the first delay circuit comprising an other first holding circuit to hold the switching request signal to be sent to the first information transmission system when the frame pulse is received, the second internal switching circuit operating in synchronization with the timing pulse for the second information transmission system, and an other second holding circuit to hold the switching request signal fed by the other first holding circuit when the timing pulse is received. 5. The non-break change-over device defined in claim 4, wherein the first and second holding circuits comprise flip-flops. 6. The non-break change-over device defined in claim 5, wherein the flip-flops are D flip-flops. 7. A non-break change-over device for complementarily switching first and second information transmission systems between an active state and a standby state and for constituting a redund

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Network switch with head of line input buffer queue clearing

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Network switch with head of line input buffer queue clearing

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이 특허에 인용된 특허 (7)

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