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A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and bein

A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

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A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and bein

A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell. ore the data bits, the first set of latches further including a serial output terminal coupled to a respective data bus terminal, a serial clock terminal receiving a clock signal, a first control terminal receiving a first shift control signal allowing the data bits to be shifted out of the first set of latches responsive to the clock signal, and an output terminal generating at least one first status signal indicative of the operating state of the first set of latches; and a first flip-flop set responsive to an initiate signal and reset responsive to a first status signal indicating that all of the data bits stored in the first set of latches have been shifted out of the first set of latches responsive to the serial clock signal, the flip-flop having an output terminal coupled to the first control terminal to apply a first shift control signal to the first control terminal to allow the data bits to be shifted out of the first set of latches when the first flip-flop is set; a second set of latches having a set of M parallel input terminals coupled to the second bus to receive and store the data bits, the second set of latches further including a serial output terminal coupled to a respective data bus terminal, a serial clock terminal receiving a clock signal, a control terminal receiving a second shift control signal allowing the data bits to be shifted out of the second set of latches responsive to the clock signal, and an output terminal generating at least one second status signal indicative of the operating state of the second set of latches; and a second flip-flop set responsive to the first status signal indicating that all of the data bits stored in the first set of latches have been shifted out of the first set of latches and reset responsive to a second status signal indicating that all of the data bits stored in the second set of latches have been shifted out of the second set of latches responsive to the serial clock signal, the second flip-flop having an output terminal coupled to the control terminal to apply a second shift control signal to the second control terminal to allow the data bits to be shifted out of the second set of latches when the second flip-flop is set. 6. The memory device data path of claim 1, wherein the storage device stores 2N bits of data in the first operating mode and N bits of data in the second operating mode. 7. A memory device, comprising: an array of memory cells arranged in rows and columns; a row address decoder coupled to receive a row address signal and to enable a corresponding row of memory cells in the array; a column address decoder coupled to receive a column address signal and to enable a corresponding column of memory cells in the array; a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands; and a read data path, comprising: a first bus coupled to receive N/2 data bits from the array; a second bus coupled to receive N/2 data bits from the array; a first set of N/2M parallel-to-serial converters coupled to the first bus, each of the parallel-to-serial converters in the first set having M input terminals coupled to receive M respective bits from the first bus, the parallel-to-serial converters in the first set having respective serial output terminals coupled to a first set of N/2M respective data bus terminals, each of the N/2M parallel-to-serial converters in the first set being operable in a first operating mode to read 2 sets of data from the array each containing M bits, the M bits in each set being coupled through the first bus, the first set of parallel-to-serial converters further being operable in the first operating mode to apply N/2M bursts each containing 2M bits to respective data bus terminals in the first set; and a second set of N/2M parallel-to-serial converters coupled to the first and second buses, each of the parallel-to-serial converters in the