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A CDMA communication system supports designated mode data bursts on a reverse link contention based channel from a subscriber unit to a base station. The reverse link contention based channel also supports contention-based transmissions from the subscriber unit to the base station. When transmission

A CDMA communication system supports designated mode data bursts on a reverse link contention based channel from a subscriber unit to a base station. The reverse link contention based channel also supports contention-based transmissions from the subscriber unit to the base station. When transmissions are scheduled and serviced in the designated mode data burst, collisions are avoided. Further, because setting up the designated mode data bursts on the reverse link contention based channel require little overhead as compared to the setup of a traffic channel the CDMA system is operated at a greater efficiency. The reverse link contention based channel may be a Reverse Common Control Channel, a Reverse Access Channel or another contention-based channel. Designated mode data bursts on the reverse link contention based channel may consume a single slot or multiple slots. The number of slots consumed in the designated mode data bursts depends upon the volume of data the subscriber unit has to transmit to the base station. The subscriber unit may state the amount of data it desires to transmit in the designated mode data burst. Based upon this stated amount, the base station may reserve multiple slots for the designated mode data burst. Then, the subscriber unit will transmit data during the slots.

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A CDMA communication system supports designated mode data bursts on a reverse link contention based channel from a subscriber unit to a base station. The reverse link contention based channel also supports contention-based transmissions from the subscriber unit to the base station. When transmission

A CDMA communication system supports designated mode data bursts on a reverse link contention based channel from a subscriber unit to a base station. The reverse link contention based channel also supports contention-based transmissions from the subscriber unit to the base station. When transmissions are scheduled and serviced in the designated mode data burst, collisions are avoided. Further, because setting up the designated mode data bursts on the reverse link contention based channel require little overhead as compared to the setup of a traffic channel the CDMA system is operated at a greater efficiency. The reverse link contention based channel may be a Reverse Common Control Channel, a Reverse Access Channel or another contention-based channel. Designated mode data bursts on the reverse link contention based channel may consume a single slot or multiple slots. The number of slots consumed in the designated mode data bursts depends upon the volume of data the subscriber unit has to transmit to the base station. The subscriber unit may state the amount of data it desires to transmit in the designated mode data burst. Based upon this stated amount, the base station may reserve multiple slots for the designated mode data burst. Then, the subscriber unit will transmit data during the slots. ximately a potential at the first power supply node; a fifth transistor coupled between the second output node and the second power supply node, the fifth transistor having a gate terminal coupled to a second bit line; the first output node adapted to be pre-charged to approximately a potential at the second power supply node, and the sense amplifier adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line; and a memory cell adapted to be controllably coupled to the first bit line. 7. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises first and second output nodes, the first and second output nodes of the memory cell adapted to be controllably coupled to the first and second bit lines, respectively. 8. The memory cell and sense amplifier combination of claim 7, wherein the memory cell comprises a static random access memory cell. 9. The memory cell and sense amplifier combination of claim 6, further comprising a reference signal line adapted to be controllably coupled to the second bit line. 10. The memory cell and sense amplifier combination of claim 9, wherein the memory cell comprises a dynamic random access memory cell. 11. The memory cell and sense amplifier combination of claim 9, wherein the memory cell comprises a read-only memory cell. 12. The memory cell and sense amplifier combination of claim 9, wherein the memory cell comprises a programmable read-only memory cell. 13. The memory cell and sense amplifier combination of claim 9, wherein the memory cell comprises an erasable programmable read-only memory cell. 14. The memory cell and sense amplifier combination of claim 9, wherein the memory cell comprises a Flash memory cell. 15. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises a static random access memory cell. 16. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises a dynamic random access memory cell. 17. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises a read-only memory cell. 18. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises a programmable read-only memory cell. 19. The memory cell and sense amplifier combination of claim 6, wherein the memory cell comprises an erasable programmable read-only memory cell. 20. A sensing circuit, comprising: a sense amplifier adapted to receive an input signal from a memory cell and to provide a first output signal on a first output node; and an output amplifier adapted to receive the first output signal and to provide a second output signal on a second output node, wherein the sense