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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0749498 (2000-12-22) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 469 인용 특허 : 22 |
A rechargeable battery (22). Internal to the battery is a memory (34) that has data identifying specific charging steps, sequences, that should be executed in order to apply charging current to the battery and to test the charge state of the battery. The battery memory also includes a power required
A rechargeable battery (22). Internal to the battery is a memory (34) that has data identifying specific charging steps, sequences, that should be executed in order to apply charging current to the battery and to test the charge state of the battery. The battery memory also includes a power required data field that indicates the power required to charge the battery.
A rechargeable battery (22). Internal to the battery is a memory (34) that has data identifying specific charging steps, sequences, that should be executed in order to apply charging current to the battery and to test the charge state of the battery. The battery memory also includes a power required
A rechargeable battery (22). Internal to the battery is a memory (34) that has data identifying specific charging steps, sequences, that should be executed in order to apply charging current to the battery and to test the charge state of the battery. The battery memory also includes a power required data field that indicates the power required to charge the battery. e at a same level within said windings current-inactive interval to inhibit said windings current on said stator to produce induced magnetic field. 6. The method according to claim 4, wherein said generating said induced magnetic field by said windings current on said stator is generated and controlled by a control signal, wherein said control signal outputs an inactive indication level for said windings current on said stator, wherein said windings current on said stator produces no magnetic field when said first nonoverlapping signal and said second nonoverlapping signal are at a same level. 7. The method according to claim 6, wherein said generating induced magnetic field by windings current on said motor stator is generated and controlled by a pulse width modulation signal, wherein said pulse width modulation signal separates an interval where said first nonoverlapping signal and said second nonoverlapping signal are not at a same level into a first speed controlling interval and a second speed controlling interval and outputs said inactive indication level within said windings current-inactive interval and said first speed controlling interval while outputs an active indication level within said second speed controlling interval, wherein said windings current generates induced magnetic field within said active indication level interval. 8. The method according to claim 7, wherein an interval ratio of said second speed controlling interval to said first speed controlling interval is determined by a designed speed, wherein said interval ratio is proportional to a rotating speed of said rotor. 9. The method according to claim 7, wherein said generating induced magnetic field by said windings current on said motor is generated and controlled by a speed controlling modulation signal, wherein said speed controlling modulation outputs said inactive indication level within said windings current-inactive interval and said second speed controlling interval while outputs said active indication level within said first speed controlling interval. 10. The method according to claim 4, wherein generating said induced magnetic field by windings current on said stator is generated and controlled by a driving circuit, said driving circuit comprises: a first comparator, containing two input ends and one output end of said first compartor, wherein said two input ends of said first comparator are respectively coupled to said first sensed signal and said first reference signal; a second comparator, containing two input ends and one output end of said second compartor, wherein said two input ends of said second comparator are respectively coupled to said second sensed signal and said first reference signal; and a logic gate, defining a same level interval which a level of an output signal of said first comparator is different from a level of an output signal of said second comparator to form a basis for said driving control signal, wherein said logic gate includes two logic input ends and one logic output end, wherein said two logic input ends are respectively coupled to said output end of said first comparator and said output end of said second comparator. 11. The method according to claim 10, wherein said driving circuit further comprises a pulse width modulation circuit, wherein said pulse width modulation circuit comprises a control end, a reference end, a pulse width modulation output end, a ground end and a power supplying end, wherein said control end is coupled to said logic gate, said ground end to a ground, and said power supplying end to a power supply. 12. The method according to the claim 11, wherein said pulse width modulation circuit comprises: a saw-shaped signal generation circuit, comprising said control end, said ground end, said power supplying end and a saw-shaped signal output end; and a third comparator, comprising two input ends and one output end of said third comparator, wherein said two input ends of said th ird comparator are respectively said reference end and said saw-shaped signal output end, while said output end of said third comparator is said pulse width modulation output end. 13. The method according to the claim 12 wherein said saw-shaped signal generation circuit comprises: a capacitor, including said saw-shaped signal output end and said ground end; a resistor, one end of said resistor is coupled to said saw-shaped signal output end, while the other end of said resistor is coupled to said power supplying end; and a switch, coupled to a joint of said saw-shaped signal output end of said capacitor and said ground end, and having said control end. 14. The method according to the claim 11, wherein said driving circuit further comprises a second logic gate, combining an output signal of said first logic gate and said output signal of said pulse width modulation circuit into a signal with a high level interval which is composed of a high level interval of said output signal of said first logic gate and a high level interval of said output signal of said pulse width modulation circuit, forming a basis for said driving control signal, wherein said second logic gate includes two input ends and an output end of said second logic gate, wherein said two input ends of said second logic gate are respectively coupled to said output end of said pulse width modulation and said output end of said first logic gate. 15. The method according to claim 14, wherein said second logic gate is an OR gate. 16. The method according to claim 15, wherein said driving circuit further comprises an inverter, said inverter comprises an input end and an output end of said inverter, wherein said input end of said inverter is coupled to said output end of said OR gate. 17. The method according to claim 1, wherein said specific angular distance from said critical angular position is determined by comparing a reference signal and said first sensed signal and said second sensed signal having information of said magnetic field of said motor rotor. 18. The method according to claim 1, wherein said driving control signal is generated by accompanying with a pulse width modulation method to generate said driving control signal capable of achieving in speed control over said rotor. 19. A driving circuit for driving a brushless DC motor, receiving two sensed signals from a sensor to generate a motor driving signal, said driving circuit comprises: a first comparator, comprising two input ends and one output end of said first comparator, wherein said two input ends of said first comparator are respectively coupled to one of said two sensed signals from said sensor and a reference signal; a second comparator, comprising two input ends and one output end of said second comparator, wherein said two input ends of said second comparator are respectively coupled to the other of said two sensed signals and said reference signal; a logic gate, defining a same level interval in which a level of an output signal of said first comparator is the same as a level of an output signal of said second comparator to be as a basis of forming said motor driving signal, wherein said logic gate comprises two input ends and one output end, wherein said two logic input ends are respectively coupled to said output end of said first comparator and said output end of said second comparator; a pulse width modulation circuit coupling with said logic gate and according to said same level interval defined by said logic gate to generate a PWM signal; and a logic gate group coupling with said pulse width modulation circuit for receiving said PWM signal and according to said same level interval defined by said logic gate and said PWM signal to generate said motor driving signal. 20. The driving circuit according to claim 19, wherein said pulse width modulation circuit further comprises: a saw-shaped signal generation circuit coupling with said logic gate and according to said same
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