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A supercritical pressure water cooled reactor comprising: a reactor vessel including: a shell part for containing sub-critical pressure coolant, and an end part for containing supercritical-pressure coolant which is separated from the sub-critical pressure coolant in the reactor vessel. A core-suppo

A supercritical pressure water cooled reactor comprising: a reactor vessel including: a shell part for containing sub-critical pressure coolant, and an end part for containing supercritical-pressure coolant which is separated from the sub-critical pressure coolant in the reactor vessel. A core-support plate with through-holes, the core-support plate disposed-in and fixed to the reactor vessel so that the core-support plate divides space inside the reactor vessel into a supercritical-pressure portion and a sub-critical pressure portion. Fuel tubes with both open ends fixed to the through-holes, the open ends being communicated to the supercritical-pressure portion, outside of the fuel tubes being disposed in the sub-critical pressure portion; and nuclear fuel assemblies disposed in the fuel tubes.

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A supercritical pressure water cooled reactor comprising: a reactor vessel including: a shell part for containing sub-critical pressure coolant, and an end part for containing supercritical-pressure coolant which is separated from the sub-critical pressure coolant in the reactor vessel. A core-suppo

A supercritical pressure water cooled reactor comprising: a reactor vessel including: a shell part for containing sub-critical pressure coolant, and an end part for containing supercritical-pressure coolant which is separated from the sub-critical pressure coolant in the reactor vessel. A core-support plate with through-holes, the core-support plate disposed-in and fixed to the reactor vessel so that the core-support plate divides space inside the reactor vessel into a supercritical-pressure portion and a sub-critical pressure portion. Fuel tubes with both open ends fixed to the through-holes, the open ends being communicated to the supercritical-pressure portion, outside of the fuel tubes being disposed in the sub-critical pressure portion; and nuclear fuel assemblies disposed in the fuel tubes. ngle-pole RC filter. 3. The control loop of claim 1, further comprising: a divider coupled to the oscillator and configured to receive and divide the oscillator signal to generate the reference signal. 4. The control loop of claim 1, wherein the input signal is a serial data stream. 5. The control loop of claim 4, wherein the serial data stream has a data rate of at least 2.488 GHz. 6. The control loop of claim 1, wherein the detector is configured to provide a first signal and a second signal, and wherein the first signal is indicative of a phase advance of the input signal relative to the reference signal and the second signal is indicative of a phase advance of the reference signal relative to the input signal. 7. The control loop of claim 1, wherein the detector is a phase detector. 8. The control loop of claim 1, wherein the detector is a frequency detector. 9. The control loop of claim 1, wherein the detector and gm amplifier are implemented using CMOS technology. 10. The control loop of claim 1, wherein the detector and gm amplifier are implemented using differential circuits. 11. The control loop of claim 1, wherein the gm amplifier includes: a differential amplifier configured to receive the filtered signal; and a current load circuit coupled to the differential amplifier and configured to provide the current output signal. 12. The control loop of claim 11, wherein the gm amplifier further includes: a common mode feedback circuit operative to receive the current output signal and to provide a signal that adjusts an average current of the current load circuit. 13. The control loop of claim 1, wherein the detector output signal has a peak-to-peak signal swing of less than one volt. 14. The control loop of claim 1, wherein the detector, gm amplifier, and at least a portion of the loop filter and oscillator are implemented within one CMOS integrated circuit. 15. A transceiver circuit comprising the control loop of claim 1. 16. A communication system comprising the control loop of claim 1. 17. The control loop of claim 1, wherein the lowpass filter is implemented using differential circuits. 18. The control loop of claim 17, wherein the detector output signal includes a pair of up signals and a pair of down signals, the pair of up signals further including a up positive signal and a up negative signal that are opposite of each other, and the pair of down signals further including a down positive signal and a down negative signal that are opposite of each other; wherein the lowpass filter is configured to receive the pairs of up and down signals and provide the filtered signal having a positive component and a negative component; and wherein the up positive signal is coupled to the down negative signal to provide the positive component and the up negative signal is coupled to the down positive signal to provide the negative component. 19. A phase locked loop comprising: a phase detector configured to receive an input signal and a reference signal and to provide a detector output signal indicative of timing differences between the input signal and the reference signal; a lowpass filter coupled to the phase detector and configured to receive the detector output signal and to provide a filtered signal; a gm amplifier coupled to the lowpass filter and configured to receive the filtered signal and to provide a current output signal, wherein use of the filtered signal facilitates design requirements of the gm amplifier thereby improving operations thereof; a loop filter coupled to the gm amplifier and configured to receive the current output signal and to provide a control signal; and an oscillator coupled to the loop filter and configured to receive the control signal and to provide a clock signal having a frequency that is adjusted by the control signal, and wherein the reference signal is derived from the clock signal, and wherein the input signal is a serial data stream. 20. The phase locked lo op of claim 19, wherein the phase detector and gm amplifier are implemented using CMOS technology. 21. A method for generating a clock signal locked to an input signal, the method comprising: receiving the input signal and a reference signal derived from the clock signal; generating a detector output signal indicative of timing differences between the input signal and the reference signal; filtering the detector output signal with a lowpass filter to remove high frequency components; converting the filtered detector output signal to a current signal with a transconductance (gm) amplifier, wherein use of the filtered detector output signal facilitates design requirements of the gm amplifier thereby improving operations thereof; filtering the current signal with a loop filter to generate a control signal; and adjusting the frequency of an oscillator with the control signal such that the clock signal is locked to the input signal. 22. The method of claim 21, wherein the input signal is a serial data stream. 23. The method of claim 21, wherein the detector output signal has a peak-to-peak signal swing of less than one volt. 24. An interface unit for use in a communication system, comprising: a format converter operative to receive serial input data and provide parallel output data; a locked loop coupled to the format converter and configured to receive the serial input data and to provide a clock signal to the format converter, wherein the locked loop includes a detector configured to receive the serial input data and a reference signal and to provide a detector output signal indicative of a difference between the serial input data and the reference signal, a lowpass filter coupled to the detector and configured to receive the detector output signal and to provide a filtered signal; a transconductance (gm) amplifier coupled to the lowpass filter and configured to receive the filtered signal and to provide a current output signal, wherein use of the filtered signal facilitates design requirements of the gm amplifier thereby improving operations thereof; a loop filter coupled to the gm amplifier and configured to receive the current output signal and to provide a control signal, and an oscillator coupled to the loop filter and configured to receive the control signal and to provide an oscillator signal having a property that is adjusted by the control signal, and wherein the reference signal is adjusted by the oscillator signal. 25. The interface unit of claim 24, wherein the serial data stream of the serial input data has a data rate of at least 2.488 GHz. 26. A multi-section locked loop for use in a high frequency application comprising: a first loop section including a first detector configured to receive a first input signal and a first reference signal and provide a first detector output signal indicative of a difference between the first input signal and the first reference signal, a lowpass filter coupled to the first detector and configured to receive the first detector output signal and provide a filtered signal, and a transconductance (gm) amplifier coupled to the lowpass filter and configured to receive the filtered signal and provide a first loop output signal; a second loop section configured to receive a second input signal and a second reference signal and provide a second loop output signal indicative of a difference between the second input signal and the second reference signal; a loop filter operatively coupled to the first and second loop sections and configured to receive the first or second loop output signal and provide a control signal; and an oscillator coupled to the loop filter and configured to receive the control signal and provide an oscillator signal having a property that is adjusted by the control signal, wherein the first and second reference signals are adjusted by the oscillator signal. 27. The multi-section locked loop of claim 26, wherein the second loop secti on includes a second detector configured to receive the second input signal and the second reference signal and provide a second detector output signal indicative of a difference between the second input signal and the second reference signal, and a charge pump coupled to the second detector and configured to receive the second detector output signal and provide the second loop output signal. 28. The multi-section locked loop of claim 26, further comprising: a divider coupled to the oscillator and configured to receive the oscillator signal and provide the second reference signal; wherein the first input signal is a data stream and the second input signal is a reference clock; and wherein the oscillator signal is used by the divider to provide the second reference signal. 29. A control loop comprising: a detector configured to receive an input signal and a reference signal and to provide a detector output signal indicative of a difference between the input signal and the reference signal, the detector output signal comprising one or more digital signals; a lowpass filter coupled to the detector and configured to receive the detector output signal and to provide a filtered analog voltage signal; a transconductance (gm) amplifier connected to the lowpass filter and configured to receive the filtered analog voltage signal and to provide a current output signal, wherein use of the filtered analog voltage signal facilitates design requirements of the gm amplifier thereby improving operations thereof; a loop filter connected to the gm amplifier and configured to receive the current output signal and to provide a voltage control signal; and an oscillator coupled to the loop filter and configured to receive the voltage control signal and to provide an oscillator signal having a property that is adjusted by the voltage control signal, and wherein the reference signal is adjusted by the oscillator signal.