Method of self-synchronization of configurable elements of a programmable unit
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-001/04
G06F-009/00
출원번호
US-0537932
(2000-03-29)
우선권정보
DE-0004728 (1997-02-08)
발명자
/ 주소
Vorbach, Martin
Munch, Robert
출원인 / 주소
Pact GmbH
대리인 / 주소
Kenyon & Kenyon
인용정보
피인용 횟수 :
63인용 특허 :
131
초록▼
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
대표청구항▼
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance. d address. 8. The apparatus of claim 7, wherein said history table is indexed by performing an exclusive or of said global history and said portion of said address. 9. The apparatus of claim 7, wherein said array is indexed by concatenating said global history and said portion of said address. 10. The apparatus of claim 5, wherein said local history comprises previous branch instruction target addresses. 11. A method for performing branch prediction in a microprocessor, comprising: predicting an outcome of a branch instruction based on a global history of previous branch instruction outcomes of different branch instructions stored in a storage element; and updating said global history in said storage element in response to said predicting said out come of said branch instruction prior to resolution of said outcome of said branch instruction. 12. The method of claim 11, further comprising: predicting an outcome of a second branch instruction based on said global history stored in said storage element after said updating said global history in said storage element in response to said predicting said outcome of said first branch instruction and prior to resolution of said outcome of said first branch instruction. 13. The method of claim 12, further comprising: copying said global history in said first storage element to a second storage element prior to said updating said global history in said first storage element in response to said predicting said outcome of said first branch instruction. 14. The method of claim 13, further comprising: determining said outcome of said first branch instruction; and comparing said outcome of said first branch instruction and said prediction of said outcome of said first branch instruction to determine if said prediction of said outcome of said first branch instruction is correct; and copying said global history in said second storage element to said first storage element and updating said global history in said first storage element in response to said outcome of said first branch instruction if said prediction of said outcome of said first branch instruction is incorrect. 15. The method of claim 14, further comprising: flushing a pipeline of said microprocessor and fetching a next instruction in response to said outcome of said first branch instruction if said prediction of said outcome of said first branch instruction is incorrect. 16. The method of claim 11, further comprising: storing a local history of previous outcomes of said branch instruction in a history table; and making said prediction s of said outcomes of said branch instruction based on a combination of said global and local histories. 17. The method of claim 16, wherein said history table comprises an array of storage elements configured to store said local history, wherein said method further comprises indexing into said array at least in part by a portion of an address of said branch instruction. 18. The method of claim 17, further comprising indexing into said array as a function of said global history and said portion of said address. 19. The method of claim 18, wherein said function comprises an exclusive or of said global history and said portion of said address. 20. The method of claim 18, wherein said function comprises a concatenation of said global history and said portion of said address. 21. The method of claim 11, wherein said updating said global history in said storage element in response to said predicting said outcome of said branch instruction is performed during translation of said branch instruction. 22. A microprocessor capable of performing branch prediction, comprising: instruction fetch logic configured to fetch a branch instruction; execution logic coupled to said instruction fetch logic configured to resolve an outcome of said branch instruction; and a branch predictor coupled to said instruction fetch logic and said execution logic, comprising: a storage element
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이 특허에 인용된 특허 (131)
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