Graphics display system with unified memory architecture
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/46
G06F-013/16
출원번호
US-0712736
(2000-11-14)
발명자
/ 주소
MacInnis, Alexander G.
Tang, Chengfuh Jeffrey
Xie, Xiaodong
Patterson, James T.
Kranawetter, Greg A.
출원인 / 주소
Broadcom Corporation
대리인 / 주소
Christie, Parker & Hale, LLP
인용정보
피인용 횟수 :
6인용 특허 :
128
초록▼
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system,
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
대표청구항▼
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system,
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed. ting, vol. 3, pp. 92-105, 1986. P.M. Kogge and H.S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. on Computers, vol. C-22, No. 8, pp. 786-793, Aug. 1973. R.P. Brent and H.T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. on Computers, vol. C-31, No. 3, pp. 260-264, Mar. 1982. D. Dozza et al., "A 3.5 NS, 64 Bit, Carry-Lookahead Adder," in Proc. Intl. Symp. Circuits and Systems, pp. 297-300, 1996. J. Silberman et al., "A 1.0 GHz Single-Issue 64b PowerPC Integer Processor," IEEE Intl. Solid-State Circuits Conf., pp. 230-231, Feb. 1998. W. Liu et al., "A 250-MHz Wave Pipelined Adder in 2-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 29, No. 9, pp. 1117-1128, Sep. 1994. A. Beaumont-Smith et al., "A GaAs 32-bit Adder," IEEE Symposium Computer Arithmetic, pp. 10-17, Jul. 1997. Z. Wang et al., "Fast Adders Using Enhanced Multiple-Output Domino Logic," IEEE Journal of Solid-State Circuits, vol. 32, No. 2, pp. 206-214, Feb. 1997. G. Bewick et al., "Approaching a Nanosecond: A 32 Bit Adder," IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp. 221-226, Oct. 1988. A. Weinberger, "High-Speed Binary Adder," IBM Technical Disclosure Bulletin, vol. 24, No. 8, pp. 4393-4398, Jan. 1982.
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