초록 ▼

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer ha

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.

대표청구항 ▼

1. An integrated circuit comprising: a semiconductor substrate having a semiconductor device provided thereon; a first dielectric layer on the semiconductor substrate having a first channel opening provided therein; a first barrier layer lining the first opening; a first conductor core over th

1. An integrated circuit comprising: a semiconductor substrate having a semiconductor device provided thereon; a first dielectric layer on the semiconductor substrate having a first channel opening provided therein; a first barrier layer lining the first opening; a first conductor core over the first barrier layer filling the first opening and connect to the semiconductor device and forming a first channel; a via dielectric layer over the first dielectric layer having a via opening provided therein; a second dielectric layer over the via dielectric layer having a second channel opening provided therein; a second barrier layer lining the via and second channel openings, the second barrier layer thicker in the via opening than in the second channel opening and having an opening provided therein to the first channel; and a second conductor core to fill the via and second channel openings and form a second channel and via. 2. The integrated circuit as claimed in claim 1 wherein the first, second, and via dielectric layers are of a low dielectric constant dielectric material. 3. The integrated circuit as claimed in claim 1 wherein the first and second barrier layer are of a metal from a group consisting of tantalum, titanium, tungsten, an alloy thereof, and a compound thereof. 4. The integrated circuit as claimed in claim 1 wherein the first and second conductor cores are of a material from a group consisting of copper, aluminum, gold, silver, an alloy thereof, and a compound thereof. 5. An integrated circuit comprising: a semiconductor substrate having a semiconductor device provided thereon; a device dielectric layer on the semiconductor substrate; a first channel dielectric layer on the device dielectric layer and having a first channel opening provided therein; a first barrier layer lining the first channel opening; a first seed layer over the first barrier layer; a first conductor core filling the first channel opening and connecting to the semiconductor device and forming a first channel; a via dielectric layer over the first channel dielectric layer and having a via opening provided therein; a second channel dielectric layer over the via dielectric layer and having a second channel opening provided therein; a second barrier layer lining the via and second channel openings, the second barrier layer thicker in the via opening than in the second channel opening and having an opening provided therein to the first channel; a second seed layer over the second barrier layer; a second conductor core to fill the via and second channel openings and form a second channel and via, the via in contact with the first channel. 6. The integrated circuit as claimed in claim 5 wherein the first, second, and via dielectric layers are of a low dielectric constant dielectric material. 7. The integrated circuit as claimed in claim 5 wherein the first and second barrier layer are of a metal from a group consisting of tantalum, titanium, tungsten, an alloy thereof, and a compound thereof. 8. The integrated circuit as claimed in claim 5 wherein the first and second conductor cores are of a material from a group consisting of copper, aluminum, gold, silver, an alloy thereof, and a compound thereof. 9. The integrated circuit as claimed in claim 5 wherein the first and second seed layers are of a material from a group consisting of copper, aluminum, gold, silver, an alloy thereof, and a compound thereof.