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One cell programmable switch using non-volatile cell 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
  • G11C-016/04
출원번호 US-0872716 (2001-06-01)
발명자 / 주소
  • Sun, Albert
  • Sheu, Eric
  • Lo, Ying-Che
출원인 / 주소
  • Macronix International Co., Ltd.
대리인 / 주소
    Haynes, Mark A.Haynes Beffel & Wolfeld LLP
인용정보 피인용 횟수 : 76  인용 특허 : 41

초록

A one transistor, non-volatile programmable switch is less complex and requires less area than prior art devices. The programmable switch is used in an integrated circuit and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A single, non

대표청구항

A one transistor, non-volatile programmable switch is less complex and requires less area than prior art devices. The programmable switch is used in an integrated circuit and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A single, non

이 특허에 인용된 특허 (41)

  1. Choi Jeong-Hyeok (Seoul KRX) Shin Chul-Ho (Seoul KRX), A mask read only memory device.
  2. Ra Kyeong-Man,KRX, Charge gain stress test circuit for nonvolatile memory and test method using the same.
  3. Lawman Gary R., Configuring an FPGA using embedded memory.
  4. Trimberger Stephen M., Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution.
  5. Choi Woong Lim,KRX, Data sensing device and method for multibit memory cell.
  6. Lawman Gary R., Decoder structure and method for FPGA configuration.
  7. Nachumovsky Ishai,ILX, EEPROM array using 2-bit non-volatile memory cells with serial read operations.
  8. Agrawal Om P., Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's.
  9. Yiu Tom D. H. (Milpitas CA), Flat-cell read-only-memory integrated circuit.
  10. Peng Jack Zezhong ; Han Kyung Joon, Floating gate FPGA cell with select device on drain.
  11. Castro Hernan A. (Shingle Springs CA) Holler Mark A. (Palo Alto CA), Four quadrant synapse cell employing single column summing line.
  12. Lipp Robert J. ; Freeman Richard D. ; Broze Robert U. ; Caywood John M. ; Nolan ; III Joseph G., General purpose, non-volatile reprogrammable switch.
  13. Sun Albert C.,TWX ; Chen Chang-Lun,TWX ; Lee Chee-Horng,TWX, In-circuit programming architecture with ROM and flash memory.
  14. Turner John E. (Beaverton OR) Rutledge David L. (Beaverton OR) Darling Roy D. (Forest Grove OR), In-system programmable logic device.
  15. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  16. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between circuit metal levels.
  17. McMillan Larry D. (Colorado Springs CO) Mihara Takashi (Saitama Pref JPX) Yoshimori Hiroyuki (Kanagawa Pref. JPX) Gregory John W. (Colorado Springs CO) Paz de Araujo Carlos A. (Colorado Springs CO), Memory with ferroelectric capacitor connectable to transistor gate.
  18. Chen Shen-Li,TWX, Method for manufacturing low power high efficiency non-volatile erasable programmable memory cell structure.
  19. Pass Christopher J. ; Sansbury James D. ; Madurawe Raminda U. ; Turner John E. ; Patel Rakesh H. ; Wright Peter J., Method of margin testing programmable interconnect cell.
  20. Hecht Volker ; Saxe Timothy, Method of reducing test time for NVM cell-based FPGA.
  21. Guccione Steven A., Network configuration of programmable circuits.
  22. Josephson Gregg (Aloha OR), Non-volatile erasable and programmable interconnect cell.
  23. Bass ; Jr. Roy S. (Underhill VT) Bhattacharyya Arup (Essex Junction VT) Grise Gary D. (Colchester VT), Non-volatile memory cell having Si rich silicon nitride charge trapping layer.
  24. Kaya Cetin ; Tigelaar Howard, Non-volatile memory cell structure and process for forming same.
  25. Chen Ih-Chin, Non-volatile memory cell with oxide and nitride tunneling layers.
  26. Eitan Boaz,ILX, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping.
  27. Madurawe Raminda U. ; Sansbury James D., Nonvolatile configuration cells and cell arrays.
  28. Choi Woong-Lim,KRX, Nonvolatile memory and method of programming the same.
  29. Hsu Sheng Teng ; Lee Jong Jan, One transistor ferroelectric memory cell and method of making the same.
  30. Pass Christopher J. ; Sansbury James D. ; Madurawe Raminda U. ; Turner John E. ; Patel Rakesh H. ; Wright Peter J., Programmable interconnect junction.
  31. Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
  32. Agrawal Om (San Jose CA) Shankar Kapil (San Jose CA), Programmable logic device with subroutine stack and random access memory.
  33. Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic element interconnections for programmable logic array integrated circuits.
  34. Gupta Anil (San Jose CA) Cliff Richard G. (Santa Clara CA), Programmable transfer-devices.
  35. Iwase Taira (Kawasaki JPX), Read only memory capable of realizing high-speed read operation.
  36. El Gamal Abbas (Palo Alto CA) Chiang Steve S. S. (Saratoga CA), Reconfigurable programmable interconnect architecture.
  37. Chiu Daniel,TWX ; Yang C. C.,TWX ; Peng Peng-Yih,TWX ; Wu J. Y.,TWX ; Lai J. S.,TWX, Retainer ring for polishing head of chemical-mechanical polish machines.
  38. Yamasaki Kazuyuki (Tokyo JPX) Nishizaka Teiichiro (Tokyo JPX) Otsuki Kazutaka (Tokyo JPX), Semiconductor memory having a plurality of memory banks and sub-bit lines which are connected to a main bit line via MOS.
  39. Hotta Yasuhiro (Nara JPX), Semiconductor read only memory with paralleled selecting transistors for higher speed.
  40. Holschwandner Lowell H. (Fountain Hill PA) Rana Virendra V. S. (South Whitehall Township ; Lehigh County PA), Tungsten metallization.
  41. Eitan Boaz,ILX, Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.

이 특허를 인용한 특허 (76)

  1. Forbes,Leonard, 4FEEPROM NROM memory arrays with vertical devices.
  2. Forbes,Leonard, 4FEEPROM NROM memory arrays with vertical devices.
  3. Wirtz, II, Frank C., Apparatus and method for preinitializing logic function.
  4. Forbes, Leonard, Apparatus and method for split gate NROM memory.
  5. Forbes,Leonard, Apparatus and method for split transistor memory having improved endurance.
  6. Forbes, Leonard, Apparatus and method for trench transistor memory having different gate dielectric thickness.
  7. Forbes, Leonard, Ballistic direct injection NROM cell on strained silicon structures.
  8. Forbes, Leonard, Ballistic direct injection NROM cell on strained silicon structures.
  9. Forbes,Leonard, Ballistic direct injection NROM cell on strained silicon structures.
  10. Fowler, Michael L., Cross point switch with serializer and deserializer functions.
  11. Forbes, Leonard, Flash memory having a high-permittivity tunnel dielectric.
  12. Forbes,Leonard, Flash memory having a high-permittivity tunnel dielectric.
  13. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
  14. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
  15. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
  16. Forbes,Leonard, Fully depleted silicon-on-insulator CMOS logic.
  17. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  18. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  19. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  20. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  21. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  22. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
  23. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
  24. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
  25. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
  26. Forbes,Leonard, Method for fabricating semiconductor vertical NROM memory cells.
  27. Mihnea, Andrei, Method for programming and erasing an NROM cell.
  28. Mihnea, Andrei, Method for programming and erasing an NROM cell.
  29. Mihnea, Andrei, Method for programming and erasing an NROM cell.
  30. Mihnea,Andrei, Method for programming and erasing an NROM cell.
  31. Mihnea,Andrei, Method for programming and erasing an NROM cell.
  32. Mihnea,Andrei, Method for programming and erasing an NROM cell.
  33. Forbes,Leonard, Multi-state NROM device.
  34. Forbes,Leonard, Multi-state NROM device.
  35. Forbes,Leonard, Multi-state NROM device.
  36. Prall, Kirk, Multi-state memory cell with asymmetric charge trapping.
  37. Prall, Kirk, Multi-state memory cell with asymmetric charge trapping.
  38. Prall,Kirk, Multi-state memory cell with asymmetric charge trapping.
  39. Forbes, Leonard, NROM flash memory cell with integrated DRAM.
  40. Forbes,Leonard, NROM flash memory cell with integrated DRAM.
  41. Forbes,Leonard, NROM flash memory cell with integrated DRAM.
  42. Forbes, Leonard, NROM flash memory devices on ultrathin silicon.
  43. Forbes, Leonard, NROM flash memory devices on ultrathin silicon.
  44. Forbes,Leonard, NROM flash memory devices on ultrathin silicon.
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  46. Forbes,Leonard, NROM flash memory devices on ultrathin silicon.
  47. Forbes,Leonard, NROM flash memory devices on ultrathin silicon.
  48. Forbes,Leonard, NROM flash memory devices on ultrathin silicon.
  49. Forbes,Leonard, NROM flash memory with a high-permittivity gate dielectric.
  50. Forbes,Leonard, NROM flash memory with a high-permittivity gate dielectric.
  51. Forbes,Leonard, NROM flash memory with self-aligned structural charge separation.
  52. Forbes,Leonard, NROM flash memory with self-aligned structural charge separation.
  53. Prall, Kirk D.; Forbes, Leonard, NROM memory cell, memory array, related devices and methods.
  54. Prall, Kirk D.; Forbes, Leonard, NROM memory cell, memory array, related devices and methods.
  55. Prall, Kirk D.; Forbes, Leonard, NROM memory cell, memory array, related devices and methods.
  56. Prall, Kirk D.; Forbes, Leonard, NROM memory cell, memory array, related devices and methods.
  57. Prall,Kirk D.; Forbes,Leonard, NROM memory cell, memory array, related devices and methods.
  58. Prall,Kirk D.; Forbes,Leonard, NROM memory cell, memory array, related devices and methods.
  59. Prall,Kirk D.; Forbes,Leonard, NROM memory cell, memory array, related devices and methods.
  60. Prall,Kirk D.; Forbes,Leonard, NROM memory cell, memory array, related devices and methods.
  61. Hagishima, Daisuke; Kinoshita, Atsuhiro; Matsuzawa, Kazuya; Ikegami, Kazutaka; Nishi, Yoshifumi, Nonvolatile programmable logic switch.
  62. Smith, Michael, Trench corner effect bidirectional flash memory cell.
  63. Smith, Michael, Trench corner effect bidirectional flash memory cell.
  64. Smith,Michael, Trench corner effect bidirectional flash memory cell.
  65. Smith,Michael, Trench corner effect bidirectional flash memory cell.
  66. Smith,Michael, Trench corner effect bidirectional flash memory cell.
  67. Smith,Michael, Trench corner effect bidirectional flash memory cell.
  68. Forbes,Leonard, Vertical NROM NAND flash memory array.
  69. Forbes,Leonard, Vertical NROM NAND flash memory array.
  70. Forbes, Leonard, Vertical NROM having a storage density of 1 bit per 1F2.
  71. Forbes, Leonard, Vertical NROM having a storage density of 1 bit per 1F2.
  72. Forbes, Leonard, Vertical NROM having a storage density of 1 bit per 1F2.
  73. Forbes,Leonard, Vertical NROM having a storage density of 1 bit per 1F2.
  74. Forbes, Leonard, Vertical device 4F2 EEPROM memory.
  75. Forbes,Leonard, Vertical device 4FEEPROM memory.
  76. Forbes,Leonard, Vertical device 4FEEPROM memory.
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