초록 ▼

The preferred embodiment of a seismic sensor array includes a sheet of material and seismic sensors mounted to the sheet. In a further aspect of the present invention, the array includes devices to make the seismic sensor array portable and transportable. In another aspect of the present invention,

The preferred embodiment of a seismic sensor array includes a sheet of material and seismic sensors mounted to the sheet. In a further aspect of the present invention, the array includes devices to make the seismic sensor array portable and transportable. In another aspect of the present invention, the seismic sensor array is part of a seismic measurement recording system which includes a data collection box and a computer.

대표청구항 ▼

The preferred embodiment of a seismic sensor array includes a sheet of material and seismic sensors mounted to the sheet. In a further aspect of the present invention, the array includes devices to make the seismic sensor array portable and transportable. In another aspect of the present invention,

The preferred embodiment of a seismic sensor array includes a sheet of material and seismic sensors mounted to the sheet. In a further aspect of the present invention, the array includes devices to make the seismic sensor array portable and transportable. In another aspect of the present invention, the seismic sensor array is part of a seismic measurement recording system which includes a data collection box and a computer. ignal from said memory circuit is able to be output to the external world through said scan path circuit. 4. The semiconductor device according to claim 2, wherein a plurality of said internal potential generation circuits are provided, said plurality of internal potential generation circuits configured to generate internal potentials of levels different from each other in response to the same first level set signal, and said plurality of internal potentials are tuned at timings different from each other, and said semiconductor device further comprises: a voltage dividing circuit including a plurality of resistive elements serially connected between a line of an external power supply potential and a line of a ground potential for generating a plurality of reference potentials corresponding to said plurality of internal potentials respectively, and a switching circuit for receiving said plurality of internal potentials and said plurality of reference potentials and supplying currently tuned said internal potential and said reference potential corresponding thereto to said compare circuit. 5. The semiconductor device according to claim 4, further comprising: an internal circuit configured to receive said internal potential generated in said internal potential generation circuit and perform a prescribed operation, a plurality of signal terminals, and for transferring signals between said internal circuit and an external world, and a scan path circuit connected between two predetermined signal terminals among said plurality of signal terminals for testing said internal circuit, wherein an output signal from said internal circuit is output to the external world through said scan path circuit. 6. The semiconductor device according to claim 1, further comprising: a detection circuit configured to detect the second level set signal for generating an internal potential substantially equal to said reference potential on the basis of said signal output from said compare circuit, and wherein said memory circuit is configured to store the second level set signal detected by said detection circuit. 7. The semiconductor device according to claim 6, wherein said compare circuit is configured to output a signal of a first or second level in response to whether said internal potential generated in said internal potential generation circuit is higher or lower than said reference potential, and said detection circuit includes: a logic circuit configured to output an activation signal in response to change of the level of said signal from said compare circuit, and a gate circuit configured to receive the second level set signals generated in said signal generation circuit and configured to supply the second level set signal to said memory circuit in response to said activation signal output from said logic circuit. 8. The semiconductor device according to claim 6, further comprising: an internal circuit configured to receive said internal potential generated in said internal potential generation circuit and configured to perform a prescribed operation, a plurality of signal terminals for transferring signals between said internal circuit and an external world, and a scan path circuit connected between two predetermined signal terminals among said plurality of signal terminals for testing said internal circuit, wherein an output signal from said memory circuit is able to be output to the external world through said scan path circuit. 9. The semiconductor device according to claim 6, further comprising: a program circuit including at least one fuse for generating a third level set signal including information indicating the level of said internal potential on the basis of whether or not said fuse is blown, a switching circuit configured to supply the second level set signal generated in said signal generation circuit as said first level set signal to said internal potential generation circuit