IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0894168
(2001-06-27)
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발명자
/ 주소 |
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출원인 / 주소 |
- Rainmaker Technologies, Inc.
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대리인 / 주소 |
Weingarten, Schurgin, Gagnebin & Lebovici LLP
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인용정보 |
피인용 횟수 :
110 인용 특허 :
36 |
초록
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Serial input data is partitioned into parallel data elements prior to rotation by an invertible linear mapping. The resulting frames of parallel signal elements are sequentially transmitted over the link. After receipt from the link, the signal is demodulated and assembled into frames of parallel si
Serial input data is partitioned into parallel data elements prior to rotation by an invertible linear mapping. The resulting frames of parallel signal elements are sequentially transmitted over the link. After receipt from the link, the signal is demodulated and assembled into frames of parallel signal elements which are de-rotated by an inverse linear mapping. The recovered parallel data elements are then re-assembled into serial output data. The linear mapping employs: 1) commuting rotation matrices for convolutionally rotating data vectors into signal vectors and vice-versa; 2) filter bank polyphase rotation matrices; or 3) computationally efficient multi-rate wavelet filter banks. Coefficients of the rotation matrix of the receiver are adaptively equalized to correct for transmission path distortion. A test signal may be inserted on the transmit side for receiver synchronization or link distortion characterization.
대표청구항
▼
Serial input data is partitioned into parallel data elements prior to rotation by an invertible linear mapping. The resulting frames of parallel signal elements are sequentially transmitted over the link. After receipt from the link, the signal is demodulated and assembled into frames of parallel si
Serial input data is partitioned into parallel data elements prior to rotation by an invertible linear mapping. The resulting frames of parallel signal elements are sequentially transmitted over the link. After receipt from the link, the signal is demodulated and assembled into frames of parallel signal elements which are de-rotated by an inverse linear mapping. The recovered parallel data elements are then re-assembled into serial output data. The linear mapping employs: 1) commuting rotation matrices for convolutionally rotating data vectors into signal vectors and vice-versa; 2) filter bank polyphase rotation matrices; or 3) computationally efficient multi-rate wavelet filter banks. Coefficients of the rotation matrix of the receiver are adaptively equalized to correct for transmission path distortion. A test signal may be inserted on the transmit side for receiver synchronization or link distortion characterization. 57.1; US-6121923, 20000900, King; US-6122506, 20000900, Lau, 455/427; US-6133871, 20001000, Krasner, 342/357.06; US-6133873, 20001000, Krasner, 342/357.12; US-6133874, 20001000, Krasner, 342/357.15; US-6151353, 20001100, Harrison et al., 342/402; US-6191731, 20010200, McBurney et al.; US-6208290, 20010300, Krasner; US-6208291, 20010300, Krasner; US-6208292, 20010300, Sih, 342/357.12; US-6236354, 20010500, Krasner, 342/357.06; US-6389291, 20020500, Pande et al.; US-6421002, 20020700, Krasner; US-6427120, 20020700, Garin et al.; US-6429809, 20020800, Vayanos et al. regenerating a clock from the synchronized network for receiving data over the packet switched network, and wherein said receiving part comprises: means for deriving a clock signal from the synchronized network, means for synchronizing received data being transmitted from the packet switched network to the synchronized network, based on the derived clock signal, and wherein the receiving part is an ATM Adaption Layer (AAL) unit, and the synchronized network comprises a PSTN. 7. The transmission system of claim 6, wherein the packet switched network is an ATM network. 8. The transmission system of claim 5, wherein the synchronized circuit-switched network is a PSTN.
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